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D a ta S he e t , F e b . 20 0 3
C515C
8 - B i t S i n gl e - C h i p M i c r o c o nt r o l l e r
M i c r o c o n t r o l l er s
Never
stop
thinking.
Edition 2003-02 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 Munchen, Germany
(c) Infineon Technologies AG 2003.
All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
D a ta S he e t , F e b . 20 0 3
C515C
8 - B i t S i n gl e - C h i p M i c r o c o nt r o l l e r
M i c r o c o n t r o l l er s
Never
stop
thinking.
C515C Data Sheet Revision History: Previous Version: Page 2003-02 2000-08
Subjects (major changes since last revision)
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8-Bit Single-Chip Microcontroller
C515C
Features * Full upward compatibility with SAB 80C515A * On-chip program memory (with optional memory protection) - C515C-8R 64 Kbytes on-chip ROM - C515C-8E 64 Kbytes on-chip OTP - alternatively up to 64 Kbytes external program memory * 256 bytes on-chip RAM * 2 Kbytes of on-chip XRAM * Up to 64 Kbytes external data memory * Superset of the 8051 architecture with 8 datapointers * Up to 10 MHz external operating frequency (1 s instruction cycle time at 6 MHz external clock) * On-chip emulation support logic (Enhanced Hooks Technology) * Current optimized oscillator circuit and EMI optimized design (further features are on next page)
On-Chip Emulation Support Module
SSC (SPI) Interface Oscillator Watchdog Power Save Modes Idle/ Power down Slow down Port 7 Port 6
Full-CAN Controller 10 Bit ADC (8 inputs) Timer 2 Capture/Compare Unit Port 5 Port 4 T1
XRAM 2k x 8
RAM 256 x 8
Port 0
I/O
T0 CPU 8 Datapointer 8 Bit USART
Port 1
I/O
Port 2 Program Memory C515C-8R : 64k x 8 ROM C515C-8E : 64k x 8 OTP
I/O
Port 3
I/O
I/O
Analog/ Digital Input
I/O
I/O
MCA03646
Figure 1
C515C Functional Units
Data Sheet
1
2003-02
C515C
* Eight ports: 48 + 1 digital I/O lines, 8 analog inputs - Quasi-bidirectional port structure (8051 compatible) - Port 5 selectable for bidirectional port structure (CMOS voltage levels) * Full-CAN controller on-chip - 256 register/data bytes are located in external data memory area - max. 1 MBaud at 8 - 10 MHz operating frequency * Three 16-bit timer/counters - Timer 2 can be used for compare/capture functions * 10-bit A/D converter with multiplexed inputs and built-in self calibration * Full duplex serial interface with programmable baudrate generator (USART) * SSC synchronous serial interface (SPI compatible) - Master and slave capable - Programmable clock polarity/clock-edge to data phase relation - LSB/MSB first selectable - 2.5 MHz transfer rate at 10 MHz operating frequency * Seventeen interrupt vectors, at four priority levels selectable * Extended watchdog facilities - 15-bit programmable watchdog timer - Oscillator watchdog * Power saving modes - Slow-down mode - Idle mode (can be combined with slow-down mode) - Software power-down mode with wake-up capability through INT0 or RXDC pin - Hardware power-down mode * CPU running condition output pin * ALE can be switched off * Multiple separate VDD/VSS pin pairs * P-MQFP-80-1 package * Temperature Ranges: SAB-C515C versions: TA = 0 to 70 C SAF-C515C versions: TA = -40 to 85 C SAH-C515C versions: TA = -40 to 110 C Note: Versions for extended temperature range -40 C to 110 C (SAH-C515C) are available on request. The C515C is an enhanced, upgraded version of the SAB 80C515A 8-bit microcontroller which additionally provides a full CAN interface, a SPI compatible synchronous serial interface, extended power save provisions, additional on-chip RAM, 64K of on-chip program memory, two new external interrupts and RFI related improvements. With a maximum external clock rate of 10 MHz it achieves a 600 ns instruction cycle time (1 s at 6 MHz).
Data Sheet
2
2003-02
C515C
The C515C-8R contains a non-volatile 64 Kbytes read-only program memory. The C515C-L is identical to the C515C-8R, except that it lacks the on-chip program memory. The C515C-8E is the OTP version in the C515C microcontroller with an on-chip 64 Kbytes one-time programmable (OTP) program memory. The C515C is mounted in a P-MQFP-80-1 package. If compared to the C515C-8R and C515C-L, the C515C-8E OTP version additionally provides two features: * The wake-up from software power down mode can, additionally to the external pin P3.2/INT0 wake-up capability, also be triggered alternatively by a second pin P4.7/RXDC. * For power consumption reasons the on-chip CAN controller can be switched off. Table 1 Device C515C-LM C515C-8RM C515C-8EM Differences in Internal Program Memory of the C505 MCUs Internal Program Memory ROM
-
OTP
-
64 Kbytes -
- 64 Kbytes
Note: The term C515C refers to all versions described within this document unless otherwise noted. Ordering Information The ordering code for Infineon Technologies' microcontrollers provides an exact reference to the required product. This ordering code identifies: * The derivative itself, i.e. its function set * The specified temperature rage * The package and the type of delivery For the available ordering codes for the C515C please refer to the "Product information Microcontrollers", which summarizes all available microcontroller variants. Note: The ordering codes for the Mask-ROM versions are defined for each product after verification of the respective ROM code.
Data Sheet
3
2003-02
C515C
VAGND
VAREF
Port 0 8 Bit Digital I/O
XTAL1 XTAL2 ALE PSEN EA RESET PE/SWD HWPD CPUR
Port 1 8 Bit Digital I/O Port 2 8 Bit Digital I/O Port 3 8 Bit Digital I/O Port 4 8 Bit Digital I/O
C515C
Port 5 8 Bit Digital I/O Port 6 8 Bit Analog/ Digital Inputs Port 7 1 Bit Digital I/O
VSSE1 VDDE1 VSSE2 VDDE2 VSS1 VDD1
VSSCLK VDDCLK VSSEXT VDDEXT
MCL02714
Figure 2
Logic Symbol
Data Sheet
4
2003-02
C515C
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P5.6 P5.5 P5.4 P5.3 P5.2 P5.1 P5.0 VDDE2 HWPD VSSE2 N.C. P4.0/ADST P4.1/SCLK P4.2/SRI PE/SWD P4.3/STO P4.4/SLS P4.5/INT8 P4.6/TXDC P4.7/RXDC 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 P2.2/A10 P2.1/A9 P2.0/A8 XTAL1 XTAL2 VSSE1 VSS1 VDD1 VDDE1 P1.0/INT3/CC0 P1.1/INT4/CC1 P1.2/INT5/CC2 P1.3/INT6/CC3 P1.4/INT2 P1.5/T2EX P1.6/CLKOUT P1.7/T2 P7.0/INT7 P3.7/RD P3.6/WR
RESET N.C. VAREF VAGND P6.7/AIN7 P6.6/AIN6 P6.5/AIN5 P6.4/AIN4 P6.3/AIN3 P6.2/AIN2 P6.1/AIN1 P6.0/AIN0 VSSCLK VDDCLK P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1
P5.7 P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VSSEXT VDDEXT EA ALE PSEN CPUR P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11
C515C
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
MCP02715
Figure 3
C515C Pin Configuration P-MQFP-80-1 (top view)
Data Sheet
5
2003-02
C515C
Table 2 Symbol RESET
Pin Definitions and Functions Pin Number P-MQFP-80-1 1 I RESET A low level on this pin for the duration of two machine cycles while the oscillator is running resets the C515C. A small internal pullup resistor permits power-on reset using only a capacitor connected to VSS . Reference voltage for the A/D converter Reference ground for the A/D converter Port 6 is an 8-bit unidirectional input port to the A/D converter. Port pins can be used for digital input, if voltage levels simultaneously meet the specifications high/low input voltages and for the eight multiplexed analog inputs. Port 7 is an 1-bit quasi-bidirectional I/O port with internal pull-up resistor. When a 1 is written to P7.0 it is pulled high by an internal pull-up resistor, and in that state can be used as input. As input, P7.0 being externally pulled low will source current (IIL, in the DC characteristics) because of the internal pull-up resistor. If P7.0 is used as interrupt input, its output latch must be programmed to a one (1). The secondary function is assigned to the port 7 pin as follows: P7.0 INT7, Interrupt 7 input I/O1) Function
VAREF VAGND
P6.0-P6.7
3 4 12-5
- - I
P7.0 / INT7 23
I/O
Data Sheet
6
2003-02
C515C
Table 2 Symbol P3.0-P3.7
Pin Definitions and Functions (cont'd) Pin Number P-MQFP-80-1 15-22 I/O Port 3 is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 3 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 3 pins being externally pulled low will source current (IIL, in the DC characteristics) because of the internal pullup resistors. Port 3 also contains the interrupt, timer, serial port and external memory strobe pins that are used by various options. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. The secondary functions are assigned to the pins of port 3, as follows: P3.0 RXD Receiver data input (asynch.) or data input/output (synch.) of serial interface P3.1 TXD Transmitter data output (asynch.) or clock output (synch.) of serial interface P3.2 INT0 External interrupt 0 input / timer 0 gate control input P3.3 INT1 External interrupt 1 input / timer 1 gate control input P3.4 T0 Timer 0 counter input P3.5 T1 Timer 1 counter input P3.6 WR WR control output; latches the data byte from port 0 into the external data memory P3.7 RD RD control output; enables the external data memory I/O1) Function
15
16
17 18 19 20 21
22
Data Sheet
7
2003-02
C515C
Table 2 Symbol
Pin Definitions and Functions (cont'd) Pin Number P-MQFP-80-1 I/O1) Function I/O Port 1 is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 1 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 1 pins being externally pulled low will source current (IIL, in the DC characteristics) because of the internal pullup resistors. The port is used for the low-order address byte during program verification. Port 1 also contains the interrupt, timer, clock, capture and compare pins that are used by various options. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate (except when used for the compare functions). The secondary functions are assigned to the port 1 pins as follows: P1.0 INT3 CC0 Interrupt 3 input / compare 0 output / capture 0 input P1.1 INT4 CC1 Interrupt 4 input / compare 1 output / capture 1 input P1.2 INT5 CC2 Interrupt 5 input / compare 2 output / capture 2 input P1.3 INT6 CC3 Interrupt 6 input / compare 3 output / capture 3 input P1.4 INT2 Interrupt 2 input P1.5 T2EX Timer 2 external reload / trigger input P1.6 CLKOUT System clock output P1.7 T2 Counter 2 input XTAL2 Input to the inverting oscillator amplifier and input to the internal clock generator circuits. To drive the device from an external clock source, XTAL2 should be driven, while XTAL1 is left unconnected. Minimum and maximum high and low times as well as rise/fall times specified in the AC characteristics must be observed.
P1.0 - P1.7 31-24
31 30 29 28 27 26 25 24 XTAL2 36 I
Data Sheet
8
2003-02
C515C
Table 2 Symbol XTAL1 P2.0-P2.7
Pin Definitions and Functions (cont'd) Pin Number P-MQFP-80-1 37 38-45 O I/O XTAL1 Output of the inverting oscillator amplifier. Port 2 is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 2 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 2 pins being externally pulled low will source current (IIL, in the DC characteristics) because of the internal pullup resistors. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pullup resistors when issuing 1's. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 issues the contents of the P2 special function register. CPU Running Condition This output pin is at low level when the CPU is running and program fetches or data accesses in the external data memory area are executed. In idle mode, hardware and software power down mode, and with an active RESET signal CPUR is set to high level. CPUR can be typically used for switching external memory devices into power saving modes. The Program Store Enable output is a control signal that enables the external program memory to the bus during external fetch operations. It is activated every six oscillator periods, except during external data memory accesses. The signal remains high during internal program execution. I/O1) Function
CPUR
46
O
PSEN
47
O
Data Sheet
9
2003-02
C515C
Table 2 Symbol ALE
Pin Definitions and Functions (cont'd) Pin Number P-MQFP-80-1 48 O The Address Latch Enable output is used for latching the address into external memory during normal operation. It is activated every six oscillator periods, except during an external data memory access. ALE can be switched off when the program is executed internally. External Access Enable When held high, the C515C executes instructions always from the internal ROM. When held low, the C515C fetches all instructions from external program memory. Note: For the ROM protection version EA pin is latched during reset. I/O1) Function
EA
49
I
P0.0-P0.7
52-59
I/O
Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1's written to them float, and in that state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application it uses strong internal pullup resistors when issuing 1's. Port 0 also outputs the code bytes during program verification in the C515C. External pullup resistors are required during program verification. Port 5 is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 5 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 5 pins being externally pulled low will source current (IIL, in the DC characteristics) because of the internal pullup resistors. Port 5 can also be switched into a bidirectional mode, in which CMOS levels are provided. In this bidirectional mode, each port 5 pin can be programmed individually as input or output.
P5.0-P5.7
67-60
I/O
Data Sheet
10
2003-02
C515C
Table 2 Symbol HWPD
Pin Definitions and Functions (cont'd) Pin Number P-MQFP-80-1 69 I Hardware Power Down A low level on this pin for the duration of one machine cycle while the oscillator is running resets the C515C. A low level for a longer period will force the part to power down mode with the pins floating. Port 4 is an 8-bit quasi-bidirectional I/O port with internal pull-up resistors. Port 4 pins that have 1's written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, port 4 pins being externally pulled low will source current (IIL, in the DC characteristics) because of the internal pull-up resistors. P4 also contains the external A/D converter control pin, the SSC pins, the CAN controller input/output lines, and the external interrupt 8 input. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. The alternate functions are assigned to port 4 as follows: P4.0 ADST External A/D converter start pin P4.1 SCLK SSC Master Clock Output / SSC Slave Clock Input P4.2 SRI SSC Receive Input P4.3 STO SSC Transmit Output P4.4 SLS Slave Select Input External interrupt 8 input P4.5 INT8 P4.6 TXDC Transmitter output of the CAN controller P4.7 RXDC Receiver input of the CAN controller I/O1) Function
P4.0-P4.7
72-74, 76-80
I/O
72 73 74 76 77 78 79 80
Data Sheet
11
2003-02
C515C
Table 2 Symbol PE/SWD
Pin Definitions and Functions (cont'd) Pin Number P-MQFP-80-1 75 I Power saving mode enable / Start watchdog timer A low level on this pin allows the software to enter the power down, idle and slow down mode. In case the low level is also seen during reset, the watchdog timer function is off on default. Use of the software controlled power saving modes is blocked, when this pin is held on high level. A high level during reset performs an automatic start of the watchdog timer immediately after reset. When left unconnected this pin is pulled high by a weak internal pull-up resistor. Ground (0 V) for on-chip oscillator This pin is used for ground connection of the on-chip oscillator circuit. Supply voltage for on-chip oscillator This pin is used for power supply of the on-chip oscillator circuit. Supply voltage for I/O ports These pins are used for power supply of the I/O ports during normal, idle, and power down mode. Ground (0 V) for I/O ports These pins are used for ground connections of the I/O ports during normal, idle, and power down mode. Supply voltage for internal logic This pins is used for the power supply of the internal logic circuits during normal, idle, and power down mode. Ground (0 V) for internal logic This pin is used for the ground connection of the internal logic circuits during normal, idle, and power down mode. I/O1) Function
VSSCLK
13
-
VDDCLK
14
-
VDDE1 VDDE2 VSSE1 VSSE2
32 68 35 70
-
-
VDD1
33
-
VSS1
34
-
Data Sheet
12
2003-02
C515C
Table 2 Symbol
Pin Definitions and Functions (cont'd) Pin Number P-MQFP-80-1 50 I/O1) Function - Supply voltage for external access pins This pin is used for power supply of the I/O ports and control signals which are used during external accesses (for Port 0, Port 2, ALE, PSEN, P3.6/WR, and P3.7/RD). Ground (0 V) for external access pins This pin is used for the ground connection of the I/O ports and control signals which are used during external accesses (for Port 0, Port 2, ALE, PSEN, P3.6/WR, and P3.7/RD). Not connected These pins should not be connected.
VDDEXT
VSSEXT
51
-
N.C.
1)
2, 71
-
I = Input; O = Output
Data Sheet
13
2003-02
C515C
Oscillator Watchdog XTAL1 XTAL2 ALE PSEN EA CPUR PE/SWD HWPD RESET Timer 1 Port 1 Timer 2 Capture Compare Unit Port 2 Timer 0 Port 0 Programmable Watchdog Timer CPU 8 Datapointers Emulation Support Logic XRAM 2k x 8 OSC & Timing RAM 256 x 8 ROM/OTP 64k x 8
Multiple V DD /V SS Lines
Port 0 8 Bit Digital I/O Port 1 8 Bit Digital I/O Port 2 8 Bit Digital I/O Port 3 8 Bit Digital I/O Port 4 8 Bit Digital I/O Port 5 8 Bit Digital I/O Port 6 8 Bit Analog/ Digital Inputs Port 7 1 Bit Digital I/O
USART Baud Rate Generator SSC (SPI) Interface
256 Byte Reg./Data
Port 3
Port 4
Full-CAN Controller
Port 5
Interrupt Unit
V AREF V AGND
S&H A/D Converter 10 Bit MUX
Port 6
Port 7
C515C
MCB03647
Figure 4
Block Diagram of the C515C
Data Sheet
14
2003-02
C515C
CPU The C515C is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% three-byte instructions. With a 6 MHz crystal, 58% of the instructions are executed in 1 s (10 MHz: 600 ns). PSW Special Function Register
Bit No. MSB D7H D0H CY D6H AC D5H F0 D4H RS1 D3H RS0 D2H OV D1H F1
(D0H)
Reset Value: 00H
LSB D0H P PSW
Bit CY AC F0 RS1 RS0
Function Carry Flag Used by arithmetic instruction. Auxiliary Carry Flag Used by instructions which execute BCD operations. General Purpose Flag Register Bank select control bits These bits are used to select one of the four register banks. RS1 0 0 1 1 RS0 0 1 0 1 Function Bank 0 selected, data address 00H-07H Bank 1 selected, data address 08H-0FH Bank 2 selected, data address 10H-17H Bank 3 selected, data address 18H-1FH
OV F1 P
Overflow Flag Used by arithmetic instruction. General Purpose Flag Parity Flag Set/cleared by hardware after each instruction to indicate an odd/even number of "one" bits in the accumulator, i.e. even parity.
Data Sheet
15
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C515C
Memory Organization The C515C CPU manipulates data and operands in the following five address spaces: * * * * * * up to 64 Kbytes of internal/external program memory up to 64 Kbytes of external data memory 256 bytes of internal data memory 256 bytes CAN controller registers / data memory 2 Kbytes of internal XRAM data memory a 128 byte special function register area
Figure 5 illustrates the memory address spaces of the C515C.
Alternatively FFFF H Internal XRAM (2 KByte) F800 H Int. CAN Controller (256 Byte) F6FF H External (EA = 0) External F7FF H FFFF H
External Data Memory Internal (EA = 1)
F700 H
Indirect Address FF H Internal RAM 80 H Internal RAM
Direct Address Special Function Register 7F H FF H 80 H
0000 H "Code Space" "Data Space"
0000 H
00 H "Internal Data Space"
MCD02717
Figure 5
C515C Memory Map
Data Sheet
16
2003-02
C515C
Control of XRAM/CAN Controller Access The XRAM in the C515C is a memory area that is logically located at the upper end of the external memory space, but is integrated on the chip. Because the XRAM and the CAN controller is used in the same way as external data memory the same instruction types (MOVX) must be used for accessing the XRAM. Two bits in SFR SYSCON, XMAP0 and XMAP1, control the accesses to the XRAM and the CAN controller. SYSCON Special Function Register
Bit No. MSB 7 B1H -
(B1H)
C515C-8R Reset Value: X010XX01B C515C-8E Reset Value: X010X001B
2 1 LSB 0 SYSCON
6
5
4 RMAP
3 -
PMOD EALE
CSWO XMAP1 XMAP0
The function of the shaded bits is not described in this section.
Bit XMAP1
Function XRAM/CAN controller visible access control Control bit for RD/WR signals during XRAM/CAN Controller accesses. If addresses are outside the XRAM/CAN controller address range or if XRAM is disabled, this bit has no effect. XMAP1 = 0: The signals RD and WR are not activated during accesses to the XRAM/CAN Controller XMAP1 = 1: Ports 0, 2 and the signals RD and WR are activated during accesses to XRAM/CAN Controller. In this mode, address and data information during XRAM/CAN Controller accesses are visible externally. Global XRAM/CAN controller access enable/disable control XMAP0 = 0: The access to XRAM and CAN controller is enabled. XMAP0 = 1: The access to XRAM and CAN controller is disabled (default after reset). All MOVX accesses are performed via the external bus. Further, this bit is hardware protected.
XMAP0
Bit XMAP0 is hardware protected. If it is reset once (XRAM/CAN controller access enabled) it cannot be set by software. Only a reset operation will set the XMAP0 bit again.
Data Sheet
17
2003-02
C515C
The XRAM/CAN controller can be accessed by read/write instructions (MOVX A,DPTR, MOVX @DPTR,A), which use the 16-bit DPTR for indirect addressing. For accessing the XRAM or CAN controller, the effective address stored in DPTR must be in the range of F700H to FFFFH. The XRAM can be also accessed by read/write instructions (MOVX A,@Ri, MOVX @Ri,A), which use only an 8-bit address (indirect addressing with registers R0 or R1). Therefore, a special page register XPAGE which provides the upper address information (A8-A15) during 8-bit XRAM accesses. The behaviour of Port 0 and P2 during a MOVX access depends on the control bits XMAP0 and XMAP1 in register SYSCON and on the state of pin EA. Table 3 lists the various operating conditions.
Data Sheet
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C515C
Table 3
Behaviour of P0/P2 and RD/WR During MOVX Accesses
XMAP1, XMAP0 00 10 a) P0/P2Bus b) RD/WR active c) ext.memory is used a) P0/P2Bus (RD/WR-Data) b) RD/WR active c) XRAM is used a) P0Bus P2I/O b) RD/WR active c) ext.memory is used a) P0Bus (RD/WR-Data only) P2I/O b) RD/WR active c) XRAM is used a) P0/P2Bus b) RD/WR active c) ext.memory is used a) P0/P2Bus (RD/WR-Data) b) RD/WR active c) XRAM is used a) P0Bus P2I/O b) RD/WR active c) ext.memory is used a) P0Bus (RD/WR-Data) P2I/O b) RD/WR active c) XRAM is used X1 a) P0/P2Bus b) RD/WR active c) ext.memory is used a) P0/P2Bus b) RD/WR active c) ext.memory is used a) P0Bus P2I/O b) RD/WR active c) ext.memory is used a) P0Bus P2I/O b) RD/WR active c) ext.memory is used a) P0/P2Bus b) RD/WR active c) ext.memory is used a) P0/P2Bus b) RD/WR active c) ext.memory is used a) P0Bus P2I/O b) RD/WR active c) ext.memory is used a) P0Bus P2I/O b) RD/WR active c) ext.memory is used
EA = 0
MOVX @DPTR
DPTR < XRAM/CAN address range DPTR XRAMCAN address range
a) P0/P2Bus b) RD/WR active c) ext.memory is used a) P0/P2Bus (RD/WR-Data) b) RD/WR inactive c) XRAM is used a) P0Bus P2I/O b) RD/WR active c) ext.memory is used a) P0Bus (RD/WR-Data) P2I/O b) RD/WR inactive c) XRAM is used a) P0/P2Bus b) RD/WR active c) ext.memory is used a) P0/P2/0 b) RD/WR inactive c) XRAM is used a) P0Bus P2I/O b) RD/WR active c) ext.memory is used a) P2I/O P0/P2I/O b) RD/WR inactive c) XRAM is used
MOVX @ Ri
XPAGE < XRAMCAN addr. page range XPAGE XRAMCAN addr. page range
EA = 1
MOVX @DPTR
DPTR < XRAM/CAN address range DPTR XRAMCAN address range
MOVX @ Ri
XPAGE < XRAMCAN addr. page range XPAGE XRAMCAN addr. page range
modes compatible to 8051/C501 family
Data Sheet 19 2003-02
C515C
Reset and System Clock The reset input is an active low input at pin RESET. Since the reset is synchronized internally, the RESET pin must be held low for at least two machine cycles (12 oscillator periods) while the oscillator is running. A pullup resistor is internally connected to VDD to allow a power-up reset with an external capacitor only. An automatic reset can be obtained when VDD is applied by connecting the RESET pin to VSS via a capacitor. Figure 6 shows the possible reset circuitries.
a)
b)
& + RESET RESET
C515C
c)
C515C
+
RESET
C515C
MCS02721
Figure 6
Reset Circuitries
Figure 7 shows the recommended oscillator circiutries for crystal and external clock operation.
Data Sheet
20
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C515C
Crystal/Resonator Oscillator Mode C XTAL1
Driving from External Source
N.C.
XTAL1
2 - 10 MHz C XTAL2 External Oscillator Signal
XTAL2
Crystal Mode : C = 20 pF 10 pF (incl. stray capacitance) Resonator Mode : C = depends on selected ceramic resonator
MCT02765
Figure 7
Recommended Oscillator Circuitries
Multiple Datapointers As a functional enhancement to the standard 8051 architecture, the C515C contains eight 16-bit datapointers instead of only one datapointer. The instruction set uses just one of these datapointers at a time. The selection of the actual datapointer is done in the special function register DPSEL. Figure 8 illustrates the datapointer addressing mechanism.
----DPSEL(92 H) DPSEL .2 0 0 0 0 1 1 1 1 .1 0 0 1 1 0 0 1 1 .0 0 1 0 1 0 1 0 1
.2 .1 .0 DPTR7 Selected Datapointer DPTR 0 DPTR 1 DPTR 2 DPTR 3 DPTR 4 DPTR 5 DPTR 6 DPTR 7 External Data Memory
MCD00779
DPTR0 DPH(83 H ) DPL(82 H)
Figure 8
Data Sheet
External Data Memory Addressing using Multiple Datapointers
21 2003-02
C515C
Enhanced Hooks Emulation Concept The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers. Emulation of on-chip ROM based programs is possible, too. Each production chip has built-in logic for the support of the Enhanced Hooks Emulation Concept. Therefore, no costly bond-out chips are necessary for emulation. This also ensure that emulation and production chips are identical. The Enhanced Hooks Technology, which requires embedded logic in the C500 allows the C500 together with an EH-IC to function similar to a bond-out chip. This simplifies the design and reduces costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate all operating modes of the different versions of the C500 microcontrollers. This includes emulation of ROM, ROM with code rollover and ROMless modes of operation. It is also able to operate in single step mode and to read the SFRs after a break.
ICE-System Interface to Emulation Hardware
SYSCON PCON TCON
RESET EA ALE PSEN
RSYSCON RPCON RTCON
EH-IC
C500 MCU
Optional I/O Ports
Port 0 Port 2
Enhanced Hooks Interface Circuit
Port 3
Port 1
RPort 2 RPort 0
TEA TALE TPSEN
Target System Interface
MCS03280
Figure 9
Basic C500 MCU Enhanced Hooks Concept Configuration
Port 0, port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks Emulation Concept to control the operation of the device during emulation and to transfer informations about the program execution and data transfer between the external emulation hardware (ICE-system) and the C500 MCU.
Data Sheet 22 2003-02
C515C
Special Function Registers The registers, except the program counter and the four general purpose register banks, reside in the special function register area. The special function register area consists of two portions: the standard special function register area and the mapped special function register area. Two special function registers of the C515C (PCON1 and DIR5) are located in the mapped special function register area. For accessing the mapped special function register area, bit RMAP in special function register SYSCON must be set. All other special function registers are located in the standard special function register area which is accessed when RMAP is cleared ("0"). As long as bit RMAP is set, mapped special function register area can be accessed. This bit is not cleared by hardware automatically. Thus, when non-mapped/mapped registers are to be accessed, the bit RMAP must be cleared/set by software, respectively each. SYSCON Special Function Register
Bit No. MSB 7 B1H -
(B1H)
C515C-8R Reset Value: X010XX01B C515C-8E Reset Value: X010X001B
2 1 LSB 0 SYSCON
6
5
4 RMAP
3 -
PMOD EALE
CSWO XMAP1 XMAP0
The function of the shaded bits is not described in this section.
Bit RMAP
Function Special function register map bit RMAP = 0: The access to the non-mapped (standard) special function register area is enabled (reset value). RMAP = 1: The access to the mapped special function register area is enabled.
The 59 special function registers (SFRs) in the standard and mapped SFR area include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. The SFRs of the C515C are listed in Table 4 and Table 5. In Table 4 they are organized in groups which refer to the functional blocks of the C515C. The CANSFRs are also included in Table 4. Table 5 illustrates the contents of the SFRs in numeric order of their addresses. Table 6 list the CAN-SFRs in numeric order of their addresses.
Data Sheet
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C515C
Table 4
Block CPU
Special Function Registers - Functional Block
Symbol ACC B DPH DPL DPSEL PSW SP SYSCON1) ADCON01) ADCON1 ADDATH ADDATL IEN01) IEN11) IEN2 IP01) IP1 TCON1) T2CON1) SCON1) IRCON XPAGE SYSCON1) Name Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Data Pointer Select Register Program Status Word Register Stack Pointer System Control Register C515C-8R C515C-8E A/D Converter Control Register 0 A/D Converter Control Register 1 A/D Converter Data Register High Byte A/D Converter Data Register Low Byte Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Enable Register 2 Interrupt Priority Register 0 Interrupt Priority Register 1 Timer Control Register Timer 2 Control Register Serial Channel Control Register Interrupt Request Control Register Page Address Register for Extended on-chip XRAM and CAN Controller System Control Register C515C-8R C515C-8E Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 5 Direction Register Port 6, Analog/Digital Input Port 7 System Control Register Addr E0H2) F0H2) 83H 82H 92H D0H2) 81H B1H B1H D8H2) DCH D9H DAH A8H2) B8H2) 9AH A9H B9H 88H2) C8H2) 98H2) C0H2) 91H B1H B1H 80H2) 90H2) A0H2) B0H2) E8H2) F8H2) F8H2)4) DBH FAH B1H 86H A8H2) B8H2) A9H Contents after Reset 00H 00H 00H 00H XXXXX000B3) 00H 07H X010XX01B3) X010X001B3) 00H 0XXXX000B3) 00H 00XXXXXXB3) 00H 00H XX00X00XB3) 00H 0X000000B3) 00H 00H 00H 00H 00H X010XX01B3) X010X001B3) FFH FFH FFH FFH FFH FFH FFH - XXXXXXX1B3) X010XX01B3) X010X001B3) 00H 00H 00H 00H
A/DConverter
Interrupt System
XRAM
Ports
P0 P1 P2 P3 P4 P5 DIR5 P6 P7 SYSCON1) WDTREL IEN01) IEN11) IP01)
C515C-8R C515C-8E
Watchdog
Watchdog Timer Reload Register Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Priority Register 0
Data Sheet
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C515C
Table 4
Block Serial Channel
Special Function Registers - Functional Block (cont'd)
Symbol ADCON01) PCON1) SBUF SCON SRELL SRELH CR SR IR BTR0 BTR1 GMS0 GMS1 UGML0 UGML1 LGML0 LGML1 UMLM0 UMLM1 LMLM0 LMLM1 Name A/D Converter Control Register 0 Power Control Register Serial Channel Buffer Register Serial Channel Control Register Serial Channel Reload Register, low byte Serial Channel Reload Register, high byte Control Register Status Register Interrupt Register Bit Timing Register Low Bit Timing Register High Global Mask Short Register Low Global Mask Short Register High Upper Global Mask Long Register Low Upper Global Mask Long Register High Lower Global Mask Long Register Low Lower Global Mask Long Register High Upper Mask of Last Message Register Low Upper Mask of Last Message Register High Lower Mask of Last Message Register Low Lower Mask of Last Message Register High Message Object Registers: Message Control Register Low Message Control Register High Upper Arbitration Register Low Upper Arbitration Register High Lower Arbitration Register Low Lower Arbitration Register High Message Configuration Register Message Data Byte 0 Message Data Byte 1 Message Data Byte 2 Message Data Byte 3 Message Data Byte 4 Message Data Byte 5 Message Data Byte 6 Message Data Byte 7 Addr D8H2) 87H 99H 98H2) AAH BAH F700H F701H F702H F704H F705H F706H F707H F708H F709H F70AH F70BH F70CH F70DH F70EH F70FH F7n0H5) F7n1H5) F7n2H5) F7n3H5) F7n4H5) F7n5H5) F7n6H5) F7n7H5) F7n8H5) F7n9H5) F7nAH5) F7nBH5) F7nCH5) F7nDH5) F7nEH5) Contents after Reset 00H 00H XXH3) 00H D9H XXXXXX11B3) 101H XXH6) XXH6) UUH6) 0UUUUUUUB6) UUH6) UUU11111B6) UUH6) UUH6) UUH6) UUUUU000B6) UUH6) UUH6) UUH6) UUUUU000B6) UUH6) UUH6) UUH6) UUH6) UUH6) UUUUU000B6) UUUUUU00B6) XXH6) XXH6) XXH6) XXH6) XXH6) XXH6) XXH6) XXH6)
CAN Controller
MCR0 MCR1 UAR0 UAR1 LAR0 LAR1 MCFG DB0n DB1n DB2n DB3n DB4n DB5n DB6n DB7n
Data Sheet
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C515C
Table 4
Block SSC Interface
Special Function Registers - Functional Block (cont'd)
Symbol SSCCON STB SRB SCF SCIEN SSCMOD TCON TH0 TH1 TL0 TL1 TMOD Name SSC Control Register SSC Transmit Buffer SSC Receive Register SSC Flag Register SSC Interrupt Enable Register SSC Mode Test Register Timer 0/1 Control Register Timer 0, High Byte Timer 1, High Byte Timer 0, Low Byte Timer 1, Low Byte Timer Mode Register Comp./Capture Enable Reg. Comp./Capture Reg. 1, High Byte Comp./Capture Reg. 2, High Byte Comp./Capture Reg. 3, High Byte Comp./Capture Reg. 1, Low Byte Comp./Capture Reg. 2, Low Byte Comp./Capture Reg. 3, Low Byte Com./Rel./Capt. Reg. High Byte Com./Rel./Capt. Reg. Low Byte Timer 2, High Byte Timer 2, Low Byte Timer 2 Control Register Power Control Register Power Control Register 1 Addr 93H2) 94H 95H ABH2) ACH 96H 88H2) 8CH 8DH 8AH 8BH 89H C1H C3H C5H C7H C2H C4H C6H CBH CAH CDH CCH C8H2) Contents after Reset 07H XXH3) XXH3) XXXXXX00B3) XXXXXX00B3) 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 0XXXXXXXB3) 0XX0XXXXB3)
Timer 0/ Timer 1
Compare/ CCEN Capture Unit/ CCH1 Timer 2 CCH2 CCH3 CCL1 CCL2 CCL3 CRCH CRCL TH2 TL2 T2CON Power Save Modes
1) 2) 3) 4) 5) 6)
PCON1) PCON1
87H C515C-8R 88H7) C515C-8E 88H7)
This special function register is listed repeatedly since some bits of it also belong to other functional blocks. Bit-addressable special function registers "X" means that the value is undefined and the location is reserved. This SFR is a mapped SFR. For accessing this SFR, bit PDIR in SFR IP1 must be set. The notation "n" in the message object address definition defines the number of the related message object. "X" means that the value is undefined and the location is reserved. "U" means that the value is unchanged by a reset operation. "U" values are undefined (as "X") after a power-on reset operation. SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
7)
Data Sheet
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2003-02
C515C
Table 5
Addr. Register
Contents of the SFRs, SFRs in Numeric Order of their Addresses
Content Bit 7 after Reset1) FFH 07H 00H 00H 00H 00H 00H 0XXXXXXXB 0XX0XXXXB 00H 00H 00H 00H 00H FFH 00H XXXXX000B 07H XXH XXH 00H 00H XXH X00XX00XB FFH 00H 00H .7 .7 .7 .7 WDT PSEL SMOD TF1 EWPD EWPD GATE .7 .7 .7 .7 T2 .7 - SCEN .7 .7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
80H2) 81H 82H 83H 86H 87H 88H2) 88H3) 88H3) 89H 8AH 8BH 8CH 8DH 90H2) 91H 92H 93H 94H 95H 96H 98H2) 99H 9AH A0H2) A8H2) A9H
P0 SP DPL DPH WDTREL PCON TCON PCON14) PCON15) TMOD TL0 TL1 TH0 TH1 P1 XPAGE DPSEL SSCCON STB SRB SSCMOD SCON SBUF IEN2 P2 IEN0 IP0
.6 .6 .6 .6 .6 PDS TR1 - - C/T .6 .6 .6 .6 CLKOUT .6 - TEN .6 .6
.5 .5 .5 .5 .5 IDLS TF0 - - M1 .5 .5 .5 .5 T2EX .5 -
.4 .4 .4 .4 .4 SD TR0 - WS M0 .4 .4 .4 .4 INT2 .4 -
.3 .3 .3 .3 .3 GF1 IE1 - - GATE .3 .3 .3 .3 INT6 .3 - CPHA .3 .3 0 TB8 .3 - .3 ET1 .3
.2 .2 .2 .2 .2 GF0 IT1 - - C/T .2 .2 .2 .2 INT5 .2 .2 BRS2 .2 .2 0 RB8 .2 ESSC .2 EX1 .2
.1 .1 .1 .1 .1 PDE IE0 - - M1 .1 .1 .1 .1 INT4 .1 .1 BRS1 .1 .1 0 TI .1 ECAN .1 ET0 .1
.0 .0 .0 .0 .0 IDLE IT0 - - M0 .0 .0 .0 .0 INT3 .0 .0 BRS0 .0 .0 LSBSM RI .0 - .0 EX0 .0
MSTR CPOL .5 .5 0 SM2 .5 EX8 .5 ET2 .4 .4 0 REN .4 EX7 .4 ES .4
LOOPB TRIO SM0 .7 - .7 EAL OWDS SM1 .6 - .6 WDT
WDTS .5
Data Sheet
27
2003-02
C515C
Table 5
Addr. Register
Contents of the SFRs, SFRs in Numeric Order of their Addresses (cont'd)
Content Bit 7 after Reset1) D9H XXXXXX00B XXXXXX00B FFH .7 - - RD - - EXEN2 PDIR - EXF2 COCA H3 .7 .7 .7 .7 .7 .7 T2PS .7 .7 .7 .7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
AAH ABH ACH B0H2) B1H B1H B8H2) B9H BAH
SRELL SCF SCIEN P3
.6 - - WR
.5 - - T1
.4 - - T0
.3 - - INT1
.2 - - INT0 -
.1 WCOL WCEN TxD
.0 TC TCEN RxD
SYSCON4) X010XX01B SYSCON5) X010X001B IEN1 IP1 SRELH 00H 0X000000B XXXXXX11B 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H
PMOD EALE PMOD EALE SWDT EX6 - - TF2 COCA L3 .6 .6 .6 .6 .6 .6 I3FR .6 .6 .6 .6 .5 - IEX6
RMAP - RMAP - EX5 .4 - IEX5 EX4 .3 - IEX4
XMAP1 XMAP0
CSWO XMAP1 XMAP0 EX3 .2 - IEX3 EX2 .1 .1 IEX2 COCA H0 .1 .1 .1 .1 .1 .1 T2I1 .1 .1 .1 .1 EADC .0 .0 IADC COCA L0 .0 .0 .0 .0 .0 .0 T2I0 .0 .0 .0 .0
C0H2) IRCON C1H C2H C3H C4H C5H C6H C7H CAH CBH CCH CDH CCEN CCL1 CCH1 CCL2 CCH2 CCL3 CCH3
COCA COCA COCA COCA H2 L2 H1 L1 .5 .5 .5 .5 .5 .5 I2FR .5 .5 .5 .5 .4 .4 .4 .4 .4 .4 T2R1 .4 .4 .4 .4 .3 .3 .3 .3 .3 .3 T2R0 .3 .3 .3 .3 .2 .2 .2 .2 .2 .2 T2CM .2 .2 .2 .2
C8H2) T2CON CRCL CRCH TL2 TH2
Data Sheet
28
2003-02
C515C
Table 5
Addr. Register
Contents of the SFRs, SFRs in Numeric Order of their Addresses (cont'd)
Content Bit 7 after Reset1) 00H 00H 00H 00XXXXXXB - 0XXXX000B 00H FFH 00H FFH FFH XXXXXXX1B C5H 95H 02H9) CY BD .9 .1 .7 ADCL .7 RXDC .7 .7 .7 - 1 1 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
D0H2) PSW D8H2) ADCON0 D9H DAH DBH DCH E0H2) E8H2) F0H2) F8H2) F8H2) FAH FCH FDH FEH
1) 2) 3) 4) 5) 6) 7) 8) 9)
AC CLK .8 .0 .6 - .6 TXDC .6 .6 .6 - 1 0 0
F0 ADEX .7 - .5 - .5 INT8 .5 .5 .5 - 0 0 0
RS1 BSY .6 - .4 - .4 SLS .4 .4 .4 - 0 1 0
RS0 ADM .5 - .3 0 .3 STO .3 .3 .3 - 0 0 0
OV MX2 .4 - .2 MX2 .2 SRI .2 .2 .2 - 1 1 0
F1 MX1 .3 - .1 MX1 .1 SCLK .1 .1 .1 - 0 0 1
P MX0 .2 - .0 MX0 .0 ADST .0 .0 .0 INT7 1 1 0
ADDATH ADDATL P6 ADCON1 ACC P4 B P5 DIR56) P7 VR07)8) VR17)8) VR27)8)
"X" means that the value is undefined and the location is reserved. Bit-addressable special function registers SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. This SFR is available in the C515C-8R and C515C-L. This SFR is available in the C515C-8E. This SFR is a mapped SFR. For accessing this SFR, bit PDIR in SFR IP1 must be set. This SFR is a mapped SFR. For accessing this SFR, bit RMAP in SFR SYSCON must be set. These SFRs are read-only registers (C515C-8E only). The content of this SFR varies with the actual step of the C515C-8E (e.g. 01H for the first step).
Data Sheet
29
2003-02
C515C
Table 6
Contents of the CAN Registers in Numeric Order of their Addresses
Content Bit 7 after Reset2) 01H XXH XXH UUH 0UUU. UUUUB UUH UUU1. 1111B ID20-18 1 0 SJW TSEG2 ID28-21 1 ID28-21 ID20-13 ID12-5 ID4-0 ID28-21 ID20-18 ID12-5 ID4-0 MSGVAL RMTPND TXIE TXRQ 0 RXIE MSGLST CPUUPD ID28-21 ID20-18 ID12-5 ID4-0 DLC .7 .7 .7 .7 .7 .6 .6 .6 .6 .6 .5 .5 .5 .5 .5 .4 .4 .4 .4 .4 DIR .3 .3 .3 .3 .3 0 XTD .2 .2 .2 .2 .2 0 0 .1 .1 .1 .1 .1 0 0 .0 .0 .0 .0 .0 ID17-13 0 0 INTPND NEWDAT ID17-13 0 0 0 1 1 1 TEST BOFF Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Addr. Regisn = 1 to FH1) ter F700H F701H F702H F704H F705H F706H F707H F708H F709H F70AH F70BH F70CH F70DH F70EH F70FH F7n0H F7n1H F7n2H F7n3H F7n4H F7n5H F7n6H F7n7H F7n8H F7n9H F7nAH F7nBH CR SR IR BTR0 BTR1 GMS0 GMS1
CCE
0
0 RXOK
EIE TXOK
SIE LEC2
IE LEC1
INIT LEC0
EWRN -
INTID BRP TSEG1
UGML0 UUH UGML1 UUH LGML0 UUH LGML1 UUUU. U000B
UMLM0 UUH UMLM1 UUH LMLM0 LMLM1 MCR0 MCR1 UAR0 UAR1 LAR0 LAR1 MCFG DB0n DB1n DB2n DB3n DB4n UUH UUUU. U000B UUH UUH UUH UUH UUH UUUU. U000B UUUU. UU00B XXH XXH XXH XXH XXH
Data Sheet
30
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C515C
Table 6
Contents of the CAN Registers in Numeric Order of their Addresses (cont'd)
Content Bit 7 after Reset2) XXH XXH XXH .7 .7 .7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Addr. Regisn = 1 to FH1) ter F7nCH F7nDH F7nEH
1) 2)
DB5n DB6n DB7n
.6 .6 .6
.5 .5 .5
.4 .4 .4
.3 .3 .3
.2 .2 .2
.1 .1 .1
.0 .0 .0
The notation "n" in the address definition defines the number of the related message object. "X" means that the value is undefined and the location is reserved. "U" means that the value is unchanged by a reset operation. "U" values are undefined (as "X") after a power-on reset operation.
Data Sheet
31
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C515C
Digital I/O Ports The C515C allows for digital I/O on 49 lines grouped into 6 bidirectional 8-bit ports and one 1-bit port. Each port bit consists of a latch, an output driver and an input buffer. Read and write accesses to the I/O ports P0 through P7 are performed via their corresponding special function registers P0 to P7. The port structure of port 5 of the C515C is especially designed to operate either as a quasi-bidirectional port structure, compatible to the standard 8051-Family, or as a genuine bidirectional port structure. This port operating mode can be selected by software (setting or clearing the bit PMOD in the SFR SYSCON). The output drivers of port 0 and 2 and the input buffers of port 0 are also used for accessing external memory. In this application, port 0 outputs the low byte of the external memory address, time-multiplexed with the byte being written or read. Port 2 outputs the high byte of the external memory address when the address is 16 bits wide. Otherwise, the port 2 pins continue emitting the P2 SFR contents. Analog Input Ports Ports 6 is available as input port only and provides two functions. When used as digital inputs, the corresponding SFR P6 contains the digital value applied to the port 6 lines. When used for analog inputs the desired analog channel is selected by a three-bit field in SFR ADCON0 or SFR ADCON1. Of course, it makes no sense to output a value to these input-only ports by writing to the SFR P6. This will have no effect. If a digital value is to be read, the voltage levels are to be held within the input voltage specifications (VIL/VIH). Since P6 is not bit-addressable, all input lines of P6 are read at the same time by byte instructions. Nevertheless, it is possible to use port 6 simultaneously for analog and digital input. However, care must be taken that all bits of P6 that have an undetermined value caused by their analog function are masked.
Data Sheet
32
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C515C
Port Structure Selection of Port 5 After a reset operation of the C515C, the quasi-bidirectional 8051-compatible port structure is selected. For selection of the bidirectional (CMOS) port 5 structure the bit PMOD of SFR SYSCON must be set. Because each port 5 pin can be programmed as an input or an output, additionally, after the selection of the bidirectional mode the direction register DIR5 of port 5 must be written. This direction register is mapped to the port 5 register. This means, the port register address is equal to its direction register address. Figure 10 illustrates the port and direction register configuration.
Write to Port Enable
Internal Bus
Int. Bus, Bit 7 Write to IP 1
D PDIR R
Q
Port Register
Q
Delay: 2.5 Machine Cycles
Enable
Direction Register Read Port
Instruction sequence for the programming of the direction registers: ORL IP1, #80H ; Set bit PDIR MOV DIRx, #OYYH ; Write port x direction register with value YYH
MCS02649
Figure 10
Port Register, Direction Register
Data Sheet
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C515C
Timer / Counter 0 and 1 Timer / Counter 0 and 1 can be used in four operating modes as listed in Table 7: Table 7 Mode 0 1 2 3 Timer/Counter 0 and 1 Operating Modes Description 8-bit timer/counter with a divide-by-32 prescaler 16-bit timer/counter 0 0 TMOD M1 M0 0 1 0 1 Timer/Counter Input Clock internal external (max)
fOSC/6 x 32 fOSC/6
fOSC/12 x 32 fOSC/12
8-bit timer/counter with 8-bit 1 autoreload Timer/counter 0 used as one 8-bit timer/counter and one 8-bit timer / Timer 1 stops 1
In the "timer" function (C/T = `0') the register is incremented every machine cycle. Therefore the count rate is fOSC/6. In the "counter" function the register is incremented in response to a 1-to-0 transition at its corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a falling edge the max. count rate is fOSC/12. External inputs INT0 and INT1 (P3.2, P3.3) can be programmed to function as a gate to facilitate pulse width measurements. Figure 11 illustrates the input clock logic.
OSC
/6 C/T = 0
f OSC /6 Timer 0/1 Input Clock C/T = 1
P3.4/T0 P3.5/T1 TR0 TR1
_ <1
Control &
Gate (TMOD) P3.2/INT0 P3.3/INT1
=1
MCS03117
Figure 11
Timer/Counter 0 and 1 Input Clock Logic
Data Sheet
34
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C515C
Timer / Counter 2 with Compare/Capture/Reload The timer 2 of the C515C provides additional compare/capture/reload features, which allow the selection of the following operating modes: * Compare: up to 4 PWM signals with 16-bit/600 ns resolution * Capture: up to 4 high speed capture inputs with 600 ns resolution * Reload: modulation of timer 2 cycle time The block diagram in Figure 12 shows the general configuration of timer 2 with the additional compare/capture/reload registers. The I/O pins which can used for timer 2 control are located as multifunctional port functions at port 1.
P1.5/ T2EX P1.7/ T2
Sync. T2I0 T2I1 Sync. & /6 Reload EXEN2
EXF2
_ <1
Interrupt Request
Reload
OSC
f OSC /12 T2PS Timer 2 TL2 TH2
TF2
Compare
P1.0/ INT3/ CC0 P1.1/ INT4/ CC1 P1.2/ INT5/ CC2 P1.2/ INT6/ CC3
MCB02730
16 Bit Comparator
16 Bit Comparator
16 Bit Comparator
16 Bit Comparator
Input/ Output Control
Capture
CCL3/CCH3
CCL2/CCH2
CCL1/CCH1
CRCL/CRCH
Figure 12
Data Sheet
Timer 2 Block Diagram
35 2003-02
C515C
Timer 2 Operating Modes The timer 2, which is a 16-bit-wide register, can operate as timer, event counter, or gated timer. A roll-over of the count value in TL2/TH2 from all 1's to all 0's sets the timer overflow flag TF2 in SFR IRCON, which can generate an interrupt. The bits in register T2CON are used to control the timer 2 operation. Timer Mode: In timer function, the count rate is derived from the oscillator frequency. A prescaler offers the possibility of selecting a count rate of 1/6 or 1/12 of the oscillator frequency. Gated Timer Mode: In gated timer function, the external input pin T2 (P1.7) functions as a gate to the input of timer 2. If T2 is high, the internal clock input is gated to the timer. T2 = 0 stops the counting procedure. This facilitates pulse width measurements. The external gate signal is sampled once every machine cycle. Event Counter Mode: In the event counter function. the timer 2 is incremented in response to a 1-to-0 transition at its corresponding external input pin T2 (P1.7). In this function, the external input is sampled every machine cycle. Since it takes two machine cycles (12 oscillator periods) to recognize a 1-to-0 transition, the maximum count rate is 1/12 of the oscillator frequency. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it must be held for at least one full machine cycle. Reload of Timer 2: Two reload modes are selectable: In mode 0, when timer 2 rolls over from all 1's to all 0's, it not only sets TF2 but also causes the timer 2 registers to be loaded with the 16-bit value in the CRC register, which is preset by software. In mode 1, a 16-bit reload from the CRC register is caused by a negative transition at the corresponding input pin P1.5/T2EX. This transition will also set flag EXF2 if bit EXEN2 in SFR IEN1 has been set.
Data Sheet
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C515C
Timer 2 Compare Modes The compare function of a timer/register combination operates as follows: the 16-bit value stored in a compare or compare/capture register is compared with the contents of the timer register; if the count value in the timer register matches the stored value, an appropriate output signal is generated at a corresponding port pin and an interrupt can be generated. Compare Mode 0 In compare mode 0, upon matching the timer and compare register contents, the output signal changes from low to high. lt goes back to a low level on timer overflow. As long as compare mode 0 is enabled, the appropriate output pin is controlled by the timer circuit only and writing to the port will have no effect. Figure 13 shows a functional diagram of a port circuit when used in compare mode 0. The port latch is directly controlled by the timer overflow and compare match signals. The input line from the internal bus and the write-to-latch line of the port latch are disconnected when compare mode 0 is enabled.
Port Circuit Read Latch Compare Register Circuit Compare Reg. 16 Bit Comparator 16 Bit Timer Register Timer Circuit Timer Overflow Read Pin
MCS02661
VDD
Compare Match
Internal Bus Write to Latch
S D
Q Port Latch CLK Q R
Port Pin
Figure 13
Port Latch in Compare Mode 0
Data Sheet
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C515C
Compare Mode 1 If compare mode 1 is enabled and the software writes to the appropriate output latch at the port, the new value will not appear at the output pin until the next compare match occurs. Thus, it can be choosen whether the output signal has to make a new transition (1-to-0 or 0-to-1, depending on the actual pin-level) or should keep its old value at the time when the timer value matches the stored compare value. In compare mode 1 (see Figure 14) the port circuit consists of two separate latches. One latch (which acts as a "shadow latch") can be written under software control, but its value will only be transferred to the port latch (and thus to the port pin) when a compare match occurs.
Port Circuit Read Latch Compare Register Circuit Compare Reg. 16 Bit Comparator 16 Bit Timer Register Timer Circuit Read Pin
MCS02662
VDD
Internal Bus Compare Match Write to Latch
D Shadow Latch CLK
Q
Q Port Latch CLK Q
D
Port Pin
Figure 14
Compare Function in Compare Mode 1
Data Sheet
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C515C
Serial Interface (USART) The serial port is full duplex and can operate in four modes (one synchronous mode, three asynchronous modes) as illustrated in Table 8. Table 8 Mode 0 USART Operating Modes SCON SM0 0 SM1 0 Shift register mode, fixed baud rate Serial data enters and exits through RxD; TxD outputs the shift clock; 8-bit are transmitted/received (LSB first) 8-bit UART, variable baud rate 10 bits are transmitted (through TxD) or received (at RxD) 9-bit UART, fixed baud rate 11 bits are transmitted (through TxD) or received (at RxD) 9-bit UART, variable baud rate Like mode 2 Description
1
0
1
2
1
0
3
1
1
For clarification some terms regarding the difference between "baud rate clock" and "baud rate" should be mentioned. In the asynchronous modes the serial interfaces require a clock rate which is 16 times the baud rate for internal synchronization. Therefore, the baud rate generators/timers have to provide a "baud rate clock" (output signal in Figure 15 to the serial interface which - there divided by 16 - results in the actual "baud rate". Further, the abbreviation fOSC refers to the oscillator frequency (crystal or external clock operation). The variable baud rates for modes 1 and 3 of the serial interface can be derived either from timer 1 or from a dedicated baud rate generator (see Figure 15).
Data Sheet
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C515C
Timer 1 Overflow Baud Rate Generator (SRELH SRELL)
ADCON0.7 (BD) 0 1 Mode 1 Mode 3
SCON.7 SCON.6 (SM0/ SM1)
/2
PCON.7 (SMOD) 0 1 Baud Rate Clock
f OSC
Mode 2 /6 Mode 0 Only one mode can be selected
MCS02733
Note: The switch configuration shows the reset state.
Figure 15
Block Diagram of Baud Rate Generation for the Serial Interface
Table 9 below lists the values/formulas for the baud rate calculation of the serial interface with its dependencies of the control bits BD and SMOD. Table 9 Serial Interface - Baud Rate Dependencies Active Control Bits BD Mode 0 (Shift Register) Mode 1 (8-bit UART) Mode 3 (9-bit UART) - 0 1 SMOD - X X Baud Rate Calculation
Serial Interface Operating Modes
fOSC / 6
Controlled by timer 1 overflow: (2SMOD x timer 1 overflow rate) / 32 Controlled by baud rate generator (2SMOD x fOSC) / (32 x baud rate generator overflow rate)
Mode 2 (9-bit UART)
-
0 1
fOSC / 32 fOSC / 16
Data Sheet
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C515C
SSC Interface The C515C microcontroller provides a Synchronous Serial Channel unit, the SSC. This interface is compatible to the popular SPI serial bus interface. Figure 16 shows the block diagram of the SSC. The central element of the SSC is an 8-bit shift register. The input and the output of this shift register are each connected via a control logic to the pin P4.2 / SRI (SSC Receiver In) and P4.3 / STO (SSC Transmitter Out). This shift register can be written to (SFR STB) and can be read through the Receive Buffer Register SRB.
f OSC Clock Divider STB Clock Selection Shift Register SRB Receive Buffer Register Interrupt SCIEN Int. Enable Reg. SSCCON Control Register Control Logic SCF Status Register
P4.1/SCLK
P4.2/SRI Pin Control Logic P4.3/STO
P4.4/SLS
Internal Bus
MCB02735
Figure 16
SSC Block Diagram
The SSC has implemented a clock control circuit, which can generate the clock via a baud rate generator in the master mode, or receive the transfer clock in the slave mode. The clock signal is fully programmable for clock polarity and phase. The pin used for the clock signal is P4.1 / SCLK. When operating in slave mode, a slave select input is provided which enables the SSC interface and also will control the transmitter output. The pin used for this is P4.4 / SLS. The SSC control block is responsible for controlling the different modes and operation of the SSC, checking the status, and generating the respective status and interrupt signals.
Data Sheet
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C515C
CAN Controller The on-chip CAN controller is the functional heart which provides all resources that are required to run the standard CAN protocol (11-bit identifiers) as well as the extended CAN protocol (29-bit identifiers). It provides a sophisticated object layer to relieve the CPU of as much overhead as possible when controlling many different message objects (up to 15). This includes bus arbitration, resending of garbled messages, error handling, interrupt generation, etc. In order to implement the physical layer, external components have to be connected to the C515C. The internal bus interface connects the on-chip CAN controller to the internal bus of the microcontroller. The registers and data locations of the CAN interface are mapped to a specific 256 bytes wide address range of the external data memory area (F700H to F7FFH) and can be accessed using MOVX instructions. Figure 17 shows a block diagram of the on-chip CAN controller.
Data Sheet
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C515C
TXDC
RXDC
BTL-Configuration
Bit Timing Logic Timing Generator
CRC Gen./Check
TX/RX Shift Register Messages
Messages Handlers
Intelligent Memory Interrupt Register
Clocks (to all) Control
Status + Control
Bit Stream Processor Status Register Error Management Logic
MCB02736
to internal Bus
Figure 17
CAN Controller Block Diagram
The TX/RX Shift Register holds the destuffed bit stream from the bus line to allow the parallel access to the whole data or remote frame for the acceptance match test and the parallel transfer of the frame to and from the Intelligent Memory. The Bit Stream Processor (BSP) is a sequencer controlling the sequential data stream between the TX/RX Shift Register, the CRC Register, and the bus line. The BSP also controls the EML and the parallel data stream between the TX/RX Shift Register and the Intelligent Memory such that the processes of reception, arbitration, transmission, and error signalling are performed according to the CAN protocol. Note that the automatic retransmission of messages which have been corrupted by noise or other external error conditions on the bus line is handled by the BSP.
Data Sheet
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C515C
The Cyclic Redundancy Check Register (CRC) generates the Cyclic Redundancy Check code to be transmitted after the data bytes and checks the CRC code of incoming messages. This is done by dividing the data stream by the code generator polynomial. The Error Management Logic (EML) is responsible for the fault confinement of the CAN device. Its counters, the Receive Error Counter and the Transmit Error Counter, are incremented and decremented by commands from the Bit Stream Processor. According to the values of the error counters, the CAN controller is set into the states error active, error passive and busoff. The Bit Timing Logic (BTL) monitors the busline input RXDC and handles the busline related bit timing according to the CAN protocol. The BTL synchronizes on a recessive to dominant busline transition at Start of Frame (hard synchronization) and on any further recessive to dominant busline transition, if the CAN controller itself does not transmit a dominant bit (resynchronization). The BTL also provides programmable time segments to compensate for the propagation delay time and for phase shifts and to define the position of the Sample Point in the bit time. The programming of the BTL depends on the baudrate and on external physical delay times. The Intelligent Memory (CAM/RAM array) provides storage for up to 15 message objects of maximum 8 data bytes length. Each of these objects has a unique identifier and its own set of control and status bits. After the initial configuration, the Intelligent Memory can handle the reception and transmission of data without further CPU actions. Switch-off Capability of the CAN Controller (C515C-8E only) For power consumption reasons, the on-chip CAN controller in the C515C-8E can be switched off by setting bit CSWO (bit 2) in SFR SYSCON. When the CAN controller is switched off its clock signal is turned off and the operation of the CAN controller is stopped. This switch-off state of the CAN controller is equal to its state in software power down mode. After clearing bit CSWO again the CAN controller has to be reconfigured.
Data Sheet
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C515C
10-Bit A/D Converter The C515C includes a high performance / high speed 10-bit A/D-Converter (ADC) with 8 analog input channels. It operates with a successive approximation technique and uses self calibration mechanisms for reduction and compensation of offset and linearity errors. The A/D converter provides the following features: * * * * * * * 8 multiplexed input channels (port 6), which can also be used as digital inputs 10-bit resolution Single or continuous conversion mode Internal or external start-of-conversion trigger capability Interrupt request generation after each conversion Using successive approximation conversion technique via a capacitor array Built-in hidden calibration of offset and linearity errors
The main functional blocks of the A/D converter are shown in Figure 19. The A/D converter uses basically two clock signals for operation: the input clock fIN (= 1/tIN) and the conversion clock fADC (= 1/tADC). These clock signals are derived from the C515C system clock fOSC which is applied at the XTAL pins. The input clock fIN is equal to fOSC. The conversion clock is limited to a maximum frequency of 2 MHz and therefore must be adapted to fOSC by programming the conversion clock prescaler. The table in Figure 18 shows the prescaler ratios and the resulting A/D conversion times which must be selected for typical system clock rates.
Data Sheet
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C515C
ADCL f OSC
/4 MUX /8 Clock Prescaler
Conversion Clock f ADC A/D Converter Input Clock f IN
Conditions:
_ f ADC max < 2 MHz
f IN = f OSC =
1 CLP
MCS02748
MCU System Clock Rate (fOSC) 2 MHz 4 MHz 6 MHz 8 MHz 10 MHz
ADCL
Conversion Clock fADC [MHz] .5 1 1.5 2 1.25
0 0 0 0 1
Figure 18
A/D Converter Clock Selection
Data Sheet
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C515C
IEN1 (B8 H) EXEN2 SWDT IRCON (C0 H) EXF2 P6 (DB H ) P6.7 P6.6 P6.5 P6.4 P6.3 P6.2 P6.1 P6.0 TF2 IEX6 IEX5 IEX4 IEX3 IEX2 IADC EX6 EX5 EX4 EX3 EX2 EADC
Internal Bus
ADCON1 (DC H ) ADCL MX2 MX1 MX0
ADCON0 (D8 H) BD CLK ADEX BSY ADM MX2 MX1 MX0
Single/ Continuous Mode
Port 6
MUX
S&H A/D Converter
f OSC
Conversion Clock Prescaler
ADDATH ADDATL (D9H ) (DA H) .2 .3 .4 .5 .6 .7 LSB .8 .1 MSB
Conversion Clock f ADC Input Clock f IN
VAREF VAGND P4.0/ADST Write to ADDATL
Start of Conversion Internal Bus
MCB02747
Shaded bit locations are not used in ADC-functions.
Figure 19
A/D Converter Block Diagram
Data Sheet
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C515C
Interrupt System The C515C provides 17 interrupt sources with four priority levels. Seven interrupts can be generated by the on-chip peripherals (timer 0, timer 1, timer 2, serial interface, A/D converter, SSC interface, CAN controller), and ten interrupts may be triggered externally (P1.5/T2EX, P3.2/INT0, P3.3/INT1, P1.4/INT2, P1.0/INT3, P1.1/INT4, P1.2/INT5, P1.3/INT6, P7.0/INT7, P4.5/INT8). The wake-up from power-down mode interrupt has a special functionality which allows to exit from the software power-down mode by a short low pulse at pin P3.2/INT0. In the C515C the 17 interrupt sources are combined to six groups of two or three interrupt sources. Each interrupt group can be programmed to one of the four interrupt priority levels. Figure 20 to Figure 22 give a general overview of the interrupt sources and illustrate the interrupt request and control flags.
Data Sheet
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C515C
P3.2/ INT0 IT0 TCON.0 A/D Converter
Highest Priority Level IE0 TCON.1 EX0 IEN0.0 0003 H Lowest Priority Level
IADC IRCON.0
EADC IEN1.0
0043 H
IP1.0 Timer 0 Overflow Status
CAN Controller Interrupt Sources
IP0.0
TF0 TCON.5
ET0 IEN0.1
000B H
Polling Sequence
SIE CR.2 Error EIE CR.3 Message Transmit Message Receive
_ <1
IE CR.1
ECAN IEN2.1
008B H
see Note TXIE MCR0.3/2 RXIE MCR0.5/4 IEX2 IRCON.1
_ <1
INTPND MCR0.0/1
P1.4/ INT2 I2FR T2CON.5 Bit addressable Request Flag is cleared by hardware
EX2 IEN1.1
004B H EAL IEN0.7 IP1.1 IP0.1
MCS02752
Note: Each of the 15 CAN controller message objects provides the bits/flags in the shaded area.
Figure 20
Interrupt Request Sources (Part 1)
Data Sheet
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C515C
P3.3/ INT1 IT1 TCON.2
Highest Priority Level IE1 TCON.3 EX1 IEN0.2 0013 H Lowest Priority Level
SSC Inerface
WCOL SCF.1 TC SCF.0
WCEN SCIEN.1
_ <1
TCEN SCIEN.0
ESSC IEN2.2
0093 H
I3FR T2CON.6
IEX3 IRCON.2
EX3 IEN1.2
0053 H
IP1.2
IP0.2
Timer 1 Overflow
TF1 TCON.7
ET1 IEN0.3
001B H
P1.1/ INT4/ CC1
IEX4 IRCON.3
EX4 IEN1.3
005B H EAL IEN0.7 IP1.3 IP0.3
Bit addressable Request Flag is cleared by hardware
Polling Sequence
MCS02753
P1.0/ INT3/ CC0
Figure 21
Interrupt Request Sources (Part 2)
Data Sheet
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C515C
USART
RI SCON.0 TI SCON.1
_ <1
Highest Priority Level ES IEN0.4 0023 H Lowest Priority Level
P7.0/ INT7 EX7 IEN2.4 P1.2/ INT5/ CC2 IEX5 IRCON.4
00A3 H
EX5 IEN1.4
0063 H
Timer 2 Overflow P1.5/ T2EX P4.5/ INT8 EXEN2 IEN1.7
TF2 IRCON.6 EXF2 IRCON.7
_ <1
ET2 IEN0.5
002B H
EX8 IEN2.5 P1.3/ INT6/ CC3 IEX6 IRCON.5
00AB H
EX6 IEN1.5
006B H EAL IEN0.7 IP1.5 IP0.5
Bit addressable Request Flag is cleared by hardware
Polling Sequence
MCS02754
IP1.4
IP0.4
Figure 22
Interrupt Request Sources (Part 3)
Data Sheet
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C515C
Table 10
Interrupt Source and Vectors Interrupt Vector Address 0003H 000BH 0013H 001BH 0023H 0043H 004BH 0053H 005BH 0063H 006BH 007BH 008BH 00A3H 00ABH 0093H Interrupt Request Flags IE0 TF0 IE1 TF1 RI / TI TF2 / EXF2 IADC IEX2 IEX3 IEX4 IEX5 IEX6 - - - - TC / WCOL
Interrupt Source External Interrupt 0 Timer 0 Overflow External Interrupt 1 Timer 1 Overflow Serial Channel A/D Converter External Interrupt 2 External Interrupt 3 External Interrupt 4 External Interrupt 5 External Interrupt 6 Wake-up from power-down mode CAN controller External Interrupt 7 External Interrupt 8 SSC interface
Timer 2 Overflow / Ext. Reload 002BH
Data Sheet
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C515C
Fail Save Mechanisms The C515C offers two on-chip peripherals which monitor the program flow and ensure an automatic "fail-safe" reaction for cases where the controller's hardware fails or the software hangs up: * A programmable watchdog timer (WDT) with variable time-out period from 512 microseconds up to approx. 1.1 seconds at 6 MHz. * An oscillator watchdog (OWD) which monitors the on-chip oscillator and forces the microcontroller into reset state in case the on-chip oscillator fails; it also provides the clock for a fast internal reset after power-on. Programmable Watchdog Timer The watchdog timer in the C515C is a 15-bit timer, which is incremented by a count rate of fOSC/12 up to fOSC/192. For programming of the watchdog timer overflow rate, the upper 7 bit of the watchdog timer can be written. Figure 23 shows the block diagram of the watchdog timer unit.
0 f OSC /6 /2 /16 WDTL 14 WDT Reset Request WDTH IP0 (A9 H) WDTS WDTPSEL 8 7
External HW Reset External HW Power-Down PE/SWD
Control Logic 76 WDT SWDT IEN0 (A8 H) IEN1 (B8 H) WDTREL (86 H)
MCB02755
0
Figure 23
Block Diagram of the Programmable Watchdog Timer
The watchdog timer can be started by software (bit SWDT) or by hardware through pin PE/SWD, but it cannot be stopped during active mode of the C515C. If the software fails to refresh the running watchdog timer an internal reset will be initiated on watchdog timer overflow. For refreshing of the watchdog timer the content of the SFR WDTREL is transferred to the upper 7-bit of the watchdog timer. The refresh sequence consists of
Data Sheet 53 2003-02
C515C
two consecutive instructions which set the bits WDT and SWDT each. The reset cause (external reset or reset caused by the watchdog) can be examined by software (flag WDTS). It must be noted, however, that the watchdog timer is halted during the idle mode and power down mode of the processor. Oscillator Watchdog The oscillator watchdog unit serves for four functions: * Monitoring of the on-chip oscillator's function The watchdog supervises the on-chip oscillator's frequency; if it is lower than the frequency of the auxiliary RC oscillator in the watchdog unit, the internal clock is supplied by the RC oscillator and the device is brought into reset; if the failure condition disappears (i.e. the on-chip oscillator has a higher frequency than the RC oscillator), the part executes a final reset phase of typ. 1 ms in order to allow the oscillator to stabilize; then the oscillator watchdog reset is released and the part starts program execution again. * Fast internal reset after power-on The oscillator watchdog unit provides a clock supply for the reset before the on-chip oscillator has started. The oscillator watchdog unit also works identically to the monitoring function. * Restart from the hardware power down mode If the hardware power down mode is terminated the oscillator watchdog has to control the correct start-up of the on-chip oscillator and to restart the program. The oscillator watchdog function is only part of the complete hardware power down sequence; however, the watchdog works identically to the monitoring function. * Control of external wake-up from software power-down mode When the software power-down mode is left by a low level at the P3.2/INT0 pin, the oscillator watchdog unit assures that the microcontroller resumes operation (execution of the power-down wake-up interrupt) with the nominal clock rate. In the power-down mode the RC oscillator and the on-chip oscillator are stopped. Both oscillators are started again when power-down mode is released. When the on-chip oscillator has a higher frequency than the RC oscillator, the microcontroller starts operation after a final delay of typ. 1 ms in order to allow the on-chip oscillator to stabilize.
Data Sheet
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C515C
EWPD (PCON1.7)
Power-Down Mode Activated Power-Down Mode Wake-Up Interrupt Internal Reset
P3.2/ INT0
Control Logic Start/ Stop RC Oscillator f RC 3 MHz Start/ Stop /2 /5 f1 Frequency Comparator f2 f2Control Logic
Delay
_ <1
XTAL1 XTAL2
On-Chip Oscillator OWDS
IP0 (A9 H)
Internal Clock
MCB02757
Figure 24
Block Diagram of the Oscillator Watchdog
Data Sheet
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C515C
Power Saving Modes The C515C provides two basic power saving modes, the idle mode and the power down mode. Additionally, a slow down mode is available. This power saving mode reduces the internal clock rate in normal operating mode and it can be also used for further power reduction in idle mode. * Idle mode The CPU is gated off from the oscillator. All peripherals are still provided with the clock and are able to work. Idle mode is entered by software and can be left by an interrupt or reset. * Power down mode The operation of the C515C is completely stopped and the oscillator is turned off. This mode is used to save the contents of the internal RAM with a very low standby current. Software power down mode: Software power down mode is entered by software and can be left by reset or by a short low pulse at pin P3.2/INT0 (or P4.7/RXDC, C515C-8E only). Hardware power down mode: Hardware power down mode is entered when the pin HWPD is put to low level. * Slow-down mode The controller keeps up the full operating functionality, but its normal clock frequency is internally divided by 32. This slows down all parts of the controller, the CPU and all peripherals, to 1/32th of their normal operating frequency. Slowing down the frequency significantly reduces power consumption. The slow down mode can be combined with the idle mode. Table 11 gives a general overview of the entry and exit conditions of the power saving modes. In the power down mode of operation, VDD can be reduced to minimize power consumption. It must be ensured, however, that VDD is not reduced before the power down mode is invoked, and that VDD is restored to its normal operating level, before the power down mode is terminated. If e.g. the idle mode is left through an interrupt, the microcontroller state (CPU, ports, peripherals) remains preserved. If a power saving mode is left by a hardware reset, the microcontroller state is disturbed and replaced by the reset state of the C515C. If WS (bit 4) is SFR PCON1 is set (C515C-8E only), pin P4.7/RXDC is alternatively selected as wake-up pin for the software power down mode. If WS (bit 4) is SFR PCON1 is cleared (C515C-8E only), pin P3.2/INT0 is selected as wake-up pin for the software power down mode. For the C515C-8R, P3.2/INT0 is always selected as wake-up pin.
Data Sheet
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C515C
Table 11 Mode
Power Saving Modes Overview Entering (2-Instruction Example) Leaving by Remarks
Idle mode
ORL PCON, #01H Occurrence of an ORL PCON, #20H interrupt from a peripheral unit Hardware Reset
CPU clock is stopped; CPU maintains their data; peripheral units are active (if enabled) and provided with clock Oscillator is stopped; contents of on-chip RAM and SFR's are maintained;
Software Power-Down Mode
ORL PCON, #02H Hardware Reset ORL PCON, #40H Short low pulse at pin P3.2/INT0 (or P4.7/RXDC, C515C-8E only) HWPD = low HWPD = high
Hardware Power-Down Mode
C515C is put into its reset state and the oscillator is stopped; ports become floating outputs
Slow Down Mode
ORL PCON, #10H ANL PCON, #0EFH Oscillator frequency is or reduced to 1/32 of its Hardware Reset nominal frequency
Data Sheet
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C515C
OTP Memory Operation (C515C-8E only) The C515C-8E contains a 64 Kbytes one-time programmable (OTP) program memory. With the C515C-8E fast programming cycles are achieved (1 byte in 100 s). Also several levels of OTP memory protection can be selected. For programming of the device, the C515C-8E must be put into the programming mode. This typically is done not in-system but in a special programming hardware. In the programming mode the C515C-8E operates as a slave device similar as an EPROM standalone memory device and must be controlled with address/data information, control lines, and an external 11.5 V programming voltage. Figure 25 shows the pins of the C515C-8E which are required for controlling of the OTP programming mode.
VDD
VSS
A0-7 A8-A15 PALE PMSEL0 PMSEL1 XTAL1 XTAL2
Port 2
Port 0
P0-7 EA/VPP PROG PRD RESET PSEN PSEL
C515C-8E
MCP03651
Figure 25
Programming Mode Configuration of the C515C-8E
Data Sheet
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C515C
C515C-8E Pin Configuration in Programming Mode
N.C. N.C. N.C. N.C. N.C. N.C. N.C. VDD N.C. VSS N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C.
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
N.C. D7 D6 D5 D4 D3 D2 D1 D0 VSS VDD EA/VPP PROG PSEN N.C. A7/A15 A6/A14 A5/A13 A4/A12 A3/A11
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 A2/A10 A1/A9 A0/A8 XTAL1 XTAL2 VSS VSS VDD VDD N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C.
C515C-8E
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
RESET N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. VSS VDD PMSEL0 PMSEL1 PSEL PRD PALE N.C.
MCP03652
Figure 26
P-MQFP-80-1 Pin Configuration of the C515C-8E in Programming Mode (top view)
Data Sheet
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C515C
The following Table 12 contains the functional description of all C515C-8E pins which are required for OTP memory programming. Table 12 Symbol RESET 1 Pin Definitions and Functions in Programming Mode Pin Number I/O1) Function I Reset This input must be at static "0" (active) level during the whole programming mode. Programming mode selection pins These pins are used to select the different access modes in programming mode. PMSEL1,0 must satisfy a setup time to the rising edge of PALE. When the logic level of PMSEL1,0 is changed, PALE must be at low level. PMSEL1 0 0 1 1 PMSEL0 0 1 0 1 Access Mode Reserved Read version bytes Program/read lock bits Program/read OTP memory byte
PMSEL0 15 PMSEL1 16
I I
PSEL
17
I
Basic programming mode select This input is used for the basic programming mode selection and must be switched according Figure 27. Programming mode read strobe This input is used for read access control for OTP memory read, version byte read, and lock bit read operations. Programming address latch enable PALE is used to latch the high address lines. The high address lines must satisfy a setup and hold time to/from the falling edge of PALE. PALE must be at low level whenever the logic level of PMSEL1,0 is changed. XTAL2 Input to the oscillator amplifier. XTAL1 Output of the inverting oscillator amplifier.
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PRD
18
I
PALE
19
I
XTAL2 XTAL1
36 37
I O
Data Sheet
C515C
Table 12 Symbol A0/A8 A7/A15 PSEN
Pin Definitions and Functions in Programming Mode (cont'd) Pin Number I/O1) Function 38 - 45 I Address lines P2.0-7 are used as multiplexed address input lines A0-A7 and A8-A15. A8-A15 must be latched with PALE. Program store enable This input must be at static "0" level during the whole programming mode. Programming mode write strobe This input is used in programming mode as a write strobe for OTP memory program and lock bit write operations. During basic programming mode selection a low level must be applied to PROG. External Access / Programming voltage This pin must be at 11.5 V (VPP) voltage level during programming of an OTP memory byte or lock bit. During an OTP memory read operation this pin must be at high level (VIH). This pin is also used for basic programming mode selection. At basic programming mode selection a low level must be applied to EA/VPP. Data lines 0-7 During programming mode, data bytes are read or written from or to the C515C-8E via the bidirectional D0-7 which are located at port 0. Circuit ground potential must be applied to these pins in programming mode. Power supply terminal must be applied to these pins in programming mode. Not Connected These pins should not be connected in programming mode.
47
I
PROG
48
I
EA/VPP
49
I
D0 - 7
52 - 58
I/O
VSS VDD
N.C.
13, 34, 35, 51, 70 14, 32, 33, 50, 69 2-12, 20-31, 46, 60-67, 69, 71-80
- - -
1)
I = Input; O = Output
Data Sheet
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C515C
C515C-8E Basic Programming Mode Selection The basic programming mode selection scheme is shown in Figure 27.
VDD
Clock (XTAL1/XTAL2) RESET
5V
Stable
"0"
PSEN
"0"
PMSEL1, 0
0.1
PROG
"0"
PRD
"1"
PSEL
PALE
"0"
VPP
EA/VPP 0V
VIH
Ready for access mode selection
During this period signals are not actively driven
MCT03653
Figure 27
C515C-8E Basic Programming Mode Selection
Data Sheet
62
2003-02
C515C
Table 13 Access Mode
Access Modes Selection EA/ PROG PRD PMSEL 1 H H 0 H
VPP
Program OTP memory byte Read OTP memory byte Program OTP lock bits Read OTP lock bits Read OTP version byte
Address (Port 2) A0-7 A8-15 -
Data (Port 0) D0-7
VPP VIH H VPP VIH H VIH
H
H
H
L
D1, D0 see Table 14 D0-7
L
H
Byte addr. of version byte
C515C-8E Lock Bits Programming / Read The C515C-8E has two programmable lock bits which, when programmed according Table 14, provide four levels of protection for the on-chip OTP code memory. The state of the lock bits can also be read.
Data Sheet
63
2003-02
C515C
Table 14 Lock Bits at D1, D0 D1 1 D0 1
Lock Bit Protection Types Protection Protection Type Level Level 0 The OTP lock feature is disabled. During normal operation of the C515C-8E, the state of the EA pin is not latched on reset. During normal operation of the C515C-8E, MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory. EA is sampled and latched on reset. An OTP memory read operation is only possible according to ROM verification mode 2, as it is defined for a protected ROM version of the C515C-8R. Further programming of the OTP memory is disabled (reprogramming security). Same as level 1, but also OTP memory read operation using ROM verification mode 2 is disabled. Same as level 2; but additionally external code execution by setting EA = low during normal operation of the C515C-8E is no more possible. External code execution, which is initiated by an internal program (e.g. by an internal jump instruction above the ROM boundary), is still possible.
1
0
Level 1
0 0
1 0
Level 2 Level 3
Data Sheet
64
2003-02
C515C
Absolute Maximum Ratings Parameter Storage temperature Voltage on VDD pins with respect to ground (VSS) Symbol min. Limit Values max. 150 6.5 -65 -0.5 -0.5 -10 - Unit Notes
TST VDD
C
V V mA mA
- - - - -
Voltage on any pin with respect VIN to ground (VSS) Input current on any pin during - overload condition Absolute sum of all input currents during overload condition Power dissipation -
VDD + 0.5
10 |100 mA|
PDISS
-
1
W
-
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for longer periods may affect device reliability. During absolute maximum rating overload conditions (VIN > VDD or VIN < VSS) the voltage on VDD pins with respect to ground (VSS) must not exceed the values defined by the absolute maximum ratings.
Data Sheet
65
2003-02
C515C
Operating Conditions Parameter Supply voltage Symbol min. Limit Values max. 5.5 5.5 0 0 -40 -40 4 70 85 110 V V V Active mode, fOSCmax = 10 MHz Power Down mode Reference voltage - 4.25 2 Ground voltage Ambient temperature: SAB-C515C Unit Notes
VDD
VSS
C
TA TA SAF-C505 TA SAH-C505 Analog reference voltage VAREF VAGND Analog ground voltage Analog input voltage VAIN fOSC XTAL clock
VSS - 0.1 VAGND
2
VDD + 0.1 V VSS + 0.2 V VAREF V
10
- - -
MHz -
Data Sheet
66
2003-02
C515C
DC Characteristics (Operating Conditions apply)
Parameter Input low voltages all except EA, RESET, HWPD EA pin RESET and HWPD pins Port 5 in CMOS mode Input high voltages all except XTAL2, RESET, and HWPD) XTAL2 pin RESET and HWPD pins Port 5 in CMOS mode Symbol min. Limit Values max. 0.2 VDD - 0.1 0.2 VDD - 0.3 0.2 VDD + 0.1 0.3 VDD V - Unit Test Condition V -
VIL VIL1 VIL2 VILC
-0.5 -0.5 -0.5 -0.5
VIH VIH1 VIH2 VIHC
0.2 VDD + 0.9 0.7 VDD 0.6 VDD 0.7 VDD - - - 2.4 0.9 VDD 2.4 0.9 VDD 0.9 VDD 0.9 VDD -10 -65 -
VDD + 0.5 VDD + 0.5 VDD + 0.5 VDD + 0.5
V 0.45 0.45 0.45 V - - - - - - -70 -650 1 A A A A
Output low voltages Ports 1, 2, 3, 4, 5, 7 (incl. CMOS) VOL Port 0, ALE, PSEN, CPUR VOL1 P4.1, P4.3 in push-pull mode VOL3 Output high voltages Ports 1, 2, 3, 4, 5, 7 Port 0 in external bus mode, ALE, PSEN, CPUR Port 5 in CMOS mode P4.1, P4.3 in push-pull mode Logic 0 input current Ports 1, 2, 3, 4, 5, 7 Logical 0-to-1 transition current Ports 1, 2, 3, 4, 5, 7 Input leakage current Port 0, EA, P6, HWPD, AIN0-7 Input low current To RESET for reset XTAL2 PE/SWD Pin capacitance Overload current Programming voltage
IOL = 1.6 mA1) IOL = 3.2 mA1) IOL = 3.75 mA1) IOH = -80 A IOH = -10 A IOH = -800 A IOH = -80 A2) IOH = -800 A IOH = -833 A VIN = 0.45 V VIN = 2 V
0.45 < VIN < VDD
VOH VOH2 VOHC VOH3 IIL ITL ILI
ILI2 ILI3 ILI4 CIO IOV VPP
- - - - - 10.9
-100 -15 -20 10 5 12.1 pF mA V
VIN = 0.45 V VIN = 0.45 V VIN = 0.45 V fc = 1 MHz, TA = 25 C
3)4)
11.5 V 5%
Data Sheet
67
2003-02
C515C
1)
Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a Schmitt-trigger, or use an address latch with a Schmitt-trigger strobe input. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9 VDD specification when the address lines are stabilizing. Overload conditions under operating conditions occur if the voltage on the respective pin exceeds the specified operating range (i.e. VOV > VDD + 0.5 V or VOV < VSS - 0.5 V). The absolute sum of input overload currents on all port pins may not exceed 50 mA. The supply voltage (VDD and VSS) must remain within the specified limits. Not 100% tested, guaranteed by design characterization.
2)
3)
4)
Data Sheet
68
2003-02
C515C
Power Supply Current Parameter Active mode Sym- Limit Values Unit Test Condition bol typ.1) max.2) C515C-8R/ 6 MHz IDD C515C-LM 10 MHz C515C-8E Idle mode 6 MHz IDD 10 MHz 11.97 18.81 11.3 17.66 6.9 10.46 3.95 4.71 4.06 4.62 4.01 4.65 3.54 3.86 3.62 4.14 26 13.74 21.10 12.94 20.10 7.87 11.87 4.70 5.50 5.03 5.75 4.77 5.53 4.46 4.90 4.21 4.77 42.9 30 30 mA mA mA mA mA mA mA mA
6) 5) 4) 3)
C515C-8R/ 6 MHz IDD C515C-LM 10 MHz C515C-8E 6 MHz IDD 10 MHz
Active mode C515C-8R/ 6 MHz IDD with slow-down C515C-LM 10 MHz enabled C515C-8E 6 MHz IDD 10 MHz Idle mode with slow-down enabled Power-down mode At EA/VPP in programming mode
1) 2) 3)
C515C-8R/ 6 MHz IDD C515C-LM 10 MHz C515C-8E C515C-8R/ C515C-LM C515C-8E C515C-8E 6 MHz IDD 10 MHz
IPD
A A
mA
VDD = 2 ... 5.5 V
7)
IPD 11.14 IDDP -
-
The typical IDD values are periodically measured at TA = +25 C and VDD = 5 V but not 100% tested. The maximum IDD values are measured under worst case conditions (TA = 0 C or -40 C and VDD = 5.5 V)
IDD (active mode) is measured with: XTAL2 driven with tCLCH, tCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VDD - 0.5 V; XTAL1 = N.C.; EA = PE/SWD = Port 0 = Port 6 = VDD; HWPD = VDD; RESET = VSS; all other pins are disconnected. IDD (idle mode) is measured with all output pins disconnected and with all peripherals disabled; XTAL2 driven with tCLCH, tCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VDD - 0.5 V; XTAL1 = N.C.; RESET = VDD; EA = VSS; Port0 = VDD; all other pins are disconnected; IDD (active mode with slow-down mode) is measured with all output pins disconnected and with all peripherals
disabled; XTAL2 driven with tCLCH, tCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VDD - 0.5 V; XTAL1 = N.C.; RESET = VDD; all other pins are disconnected; the microcontroller is put into slow-down mode by software.
4)
5)
Data Sheet
69
2003-02
C515C
6)
IDD (idle mode with slow-down mode) is measured with all output pins disconnected and with all peripherals
disabled; XTAL2 driven with tCLCH, tCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VDD - 0.5 V; XTAL1 = N.C.; RESET = VDD; EA = VSS; Port0 = VDD; all other pins are disconnected; the microcontroller is put into idle mode with slow-down enabled by software.
7)
IPD (power-down mode) is measured under following conditions: EA = RESET = Port 0 = Port 6 = VDD; XTAL1 = N.C.; XTAL2 = VSS; PE/SWD = VSS; HWPD = VDD; VAGND = VSS; VAREF = VDD; all other pins are disconnected. IPD (hardware power-down mode) is independent of any particular pin connection.
Data Sheet
70
2003-02
C515C
Power Supply Current Calculation Formulas Parameter Active mode C515C-8R/ C515C-LM C515C-8E Idle mode C515C-8R/ C515C-LM C515C-8E Active mode with slow-down enabled C515C-8R/ C515C-LM C515C-8E Idle mode with slow-down enabled C515C-8R/ C515C-LM C515C-8E Symbol Formula 1.71 x fOSC + 1.71 1.84 x fOSC + 2.7 1.59 x fOSC + 1.76 1.79 x fOSC + 2.2 0.89 x fOSC + 1.56 1.00 x fOSC + 1.87 0.19 x fOSC + 2.81 0.20 x fOSC + 3.5 0.14 x fOSC + 3.22 0.18 x fOSC + 3.95 0.16 x fOSC + 3.05 0.19 x fOSC + 3.63 0.08 x fOSC + 3.06 0.11 x fOSC + 3.8 0.13 x fOSC + 2.84 0.14 x fOSC + 3.37
IDD typ IDD max IDD typ IDD max IDD typ IDD max IDD typ IDD max IDD typ IDD max IDD typ IDD max IDD typ IDD max IDD typ IDD max
Note: fOSC is the oscillator frequency in MHz. IDD values are given in mA.
Data Sheet
71
2003-02
C515C
[mA]
25
C515C-8E C515C-LM
20
15
od eM e
10
e od
Ac ti v e
IDD max IDD typ
M
Ac tiv
I dle M
od
e
de Mo e Idl
o own M de
Slow-d
5
Idle+Slow-down
fOSC
2 4 6 8 10
[MHz]
Figure 28
IDD Diagrams of C515C-8R/C515C-LM
72 2003-02
Data Sheet
C515C
[mA]
25
C515C-8E
20
od e
15
Ac tiv e
M
IDD max IDD typ
10
Mode+ Active
Slow-d
own
Idle M
ode
5
Idle Mode+Slow-down
fOSC
2 4 6 8 10
[MHz]
Figure 29
IDD Diagrams of C515C-8E
73 2003-02
Data Sheet
C515C
A/D Converter Characteristics (Operating Conditions apply) Parameter Analog input voltage Sample time Conversion cycle time Total unadjusted error Symbol Limit Values min. max. Unit Test Condition V ns ns LSB
1)
VAIN tS tADCC
TUE
VAGND
- - - - - -
VAREF 16 x tIN 8 x tIN 96 x tIN 48 x tIN
2
- 0.25
Prescaler / 8 Prescaler / 42) Prescaler / 8 Prescaler / 43)
4)
Internal resistance of RAREF reference voltage source Internal resistance of analog source ADC input capacitance
1)
tADC / 250 k tS / 500
- 0.25 50 k pF
tADC in [ns]5)6) tS in [ns]2)6)
6)
RASRC CAIN
VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be X000H or X3FFH, respectively.
During the sample time the input capacitance CAIN can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach their final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. This parameter includes the sample time tS, the time for determining the digital result and the time for the calibration. Values for the conversion clock tADC depend on programming and can be taken from the table on the previous page. TUE is tested at VAREF = 5.0 V, VAGND = 0 V, VDD = 4.9 V. It is guaranteed by design characterization for all other voltages within the defined voltage range. If an overload condition occurs on maximum 2 not selected analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10 mA, an additional conversion error of 1/2 LSB is permissible. During the conversion the ADC's capacitance must be repeatedly charged or discharged. The internal resistance of the reference source must allow the capacitance to reach their final voltage level within the indicated time. The maximum internal resistance results from the programmed conversion timing. Not 100% tested, but guaranteed by design characterization.
2)
3)
4)
5)
6)
Data Sheet
74
2003-02
C515C
Clock Calculation Table Clock Prescaler Ratio ADCL 1 0
/8 /4
Further timing conditions:
tADC 8 x tIN 4 x tIN
tS
16 x tIN 8 x tIN
tADCC 96 x tIN 48 x tIN
tADC min = 500 ns tIN = 1 / fOSC = tCLP
Data Sheet
75
2003-02
C515C
AC Characteristics (Operating Conditions apply) (CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF) Program Memory Characteristics Parameter Symbol 10-MHz Clock Duty Cycle 0.4 to 0.6 min. ALE pulse width max. - - - 113 - - 75 - 30 - 180 min. CLP - 40 Limit Values Variable Clock 1/CLP = 2 MHz to 10 MHz max. - ns ns ns ns ns ns Unit
tLHLL Address setup to ALE tAVLL Address hold after ALE tLLAX ALE to valid instruction tLLIV
in ALE to PSEN PSEN pulse width PSEN to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address valid after PSEN Address to valid instruction in Address float to PSEN
1)
60 15 15 - 20 115 - 0 - 35 - 0
TCLHmin - 25 - TCLHmin - 25 - - 2 CLP - 87
tLLPL tPLPH tPLIV tPXIX tPXIZ1) tPXAV1) tAVIV tAZPL
TCLLmin - 20 - - CLP + TCLHmin - 30 - 0 - TCLLmin - 5 - 0
CLP + ns TCLHmin - 65 - ns
TCLLmin - 10 ns - ns
2 CLP + ns TCLHmin - 60 - ns
Interfacing the C515C to devices with float times up to 35 ns is permissible. This limited bus contention will not cause any damage to port 0 drivers.
Data Sheet
76
2003-02
C515C
External Data Memory Characteristics Parameter Symbol 10-MHz Clock Duty Cycle 0.4 to 0.6 min. RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD max. - - - 150 - 80 267 285 190 - 65 - - - 0 Limit Values Variable Clock 1/CLP= 2 MHz to 10 MHz min. 3 CLP - 70 3 CLP - 70 CLP - 15 - 0 - - - CLP + TCLLmin - 50 2 CLP - 97 TCLHmin - 25 TCLLmin - 35 max. - - - 2 CLP + TCLHmin - 90 - CLP - 20 4 CLP - 133 ns ns ns ns ns ns ns Unit
tRLRH tWLWH tLLAX2 tRLDV
230 230 48 - 0 - - - 90 103 15 5 218 13 -
tRHDX tRHDZ Data float after RD ALE to valid data in tLLDV Address to valid data tAVDV
in ALE to WR or RD Address valid to WR WR or RD high to ALE high Data valid to WR transition Data setup before WR Data hold after WR Address float after RD
ns 4 CLP + TCLHmin - 155 CLP + TCLLmin + 50 - TCLHmin + 25 - ns ns ns ns ns ns ns
tLLWL tAVWL tWHLH tQVWX tQVWH tWHQX tRLAZ
3 CLP + - TCLLmin - 122 TCLHmin - 27 - - 0
Data Sheet
77
2003-02
C515C
SSC Interface Characteristics Parameter Clock Cycle Time: Master Mode Slave Mode Clock high time Clock low time Data output delay Data output hold Data input setup Data input hold TC bit set delay External Clock Drive at XTAL2 Parameter Symbol CPU Clock = 10 MHz Duty cycle 0.4 to 0.6 min. Oscillator period CLP High time Low time Rise time Fall time Oscillator duty cycle Clock cycle TCLH TCLL 100 40 40 - - 0.4 40 max. 100 - - 12 12 0.6 60 Variable CPU Clock 1/CLP = 2 to 10 MHz min. 100 40 40 - - 40 / CLP max. 500 CLP - TCLL CLP - TCLH 12 12 1 - 40 / CLP ns ns ns ns ns - Unit Symbol min. Limit Values max. - - - - 100 - - - 8 CLP Unit
tSCLK tSCLK tSCH tSCL tD tHO tS tHI tDTC
0.4 1.0 360 360 - 0 100 100 -
s s
ns ns ns ns ns ns ns
tR tF
DC TCL
CLP x DCmin CLP x DCmax ns
Note: The 10 MHz values in the tables are given as an example for a typical duty cycle variation of the oscillator clock from 0.4 to 0.6.
Data Sheet
78
2003-02
C515C
t LHLL ALE t AVLL t LLPL t LLIV t PLIV PSEN t AZPL t LLAX t PXAV t PXIZ t PXIX t PLPH
Port 0
A0 - A7
Instr.IN
A0 - A7
t AVIV
Port 2
A8 - A15
A8 - A15
MCT00096
Figure 30
Program Memory Read Cycle
Data Sheet
79
2003-02
C515C
t WHLH ALE
PSEN t LLDV t LLWL RD t RLDV t AVLL t LLAX2 t RLAZ Port 0 A0 - A7 from Ri or DPL t AVWL t AVDV Data IN t RHDX A0 - A7 from PCL Instr. IN t RHDZ t RLRH
Port 2
P2.0 - P2.7 or A8 - A15 from DPH
A8 - A15 from PCH
MCT00097
Figure 31
Data Memory Read Cycle
Data Sheet
80
2003-02
C515C
t WHLH ALE
PSEN t LLWL WR t QVWX t AVLL t LLAX2 A0 - A7 from Ri or DPL t AVWL Port 2 P2.0 - P2.7 or A8 - A15 from DPH A8 - A15 from PCH
MCT00098
t WLWH
t WHQX t QVWH Data OUT A0 - A7 from PCL Instr.IN
Port 0
Figure 32
Data Memory Write Cycle
TCLH XTAL2 TCLL
tR
tF V IH2 V IL
CLP
MCT02704
Figure 33
External Clock Drive at XTAL2
Data Sheet
81
2003-02
C515C
t SCLK t SCL SCLK tD STO tS SRI MSB t HI MSB t HD t SCH
~ ~
~ ~
LSB
~ ~
~ ~
LSB
~ ~
t DTC TC
~ ~
MCT02417
Figure 34 Notes:
SSC Timing
1. Shown is the data/clock relationship for CPOL = CPHA = 1. The timing diagram is valid for the other cases accordingly. 2. In the case of slave mode and CPHA = 0, the output delay for the MSB applies to the falling edge of SLS (if transmitter is enabled). 3. In the case of master mode and CPHA = 0, the MSB becomes valid after the data has been written into the shift register, i.e. at least one half SCLK clock cycle before the first clock transition.
Data Sheet
82
2003-02
C515C
OTP Memory Programming Mode Characteristics
VDD = 5 V 10%; VPP = 11.5 V 5%; TA = 25 C 10 C
Parameter ALE pulse width PMSEL setup to ALE rising edge Address setup to ALE, PROG, or PRD falling edge Address hold after ALE, PROG, or PRD falling edge Address, data setup to PROG or PRD Address, data hold after PROG or PRD PMSEL setup to PROG or PRD PMSEL hold after PROG or PRD PROG pulse width PRD pulse width Address to valid data out PRD to valid data out Data hold after PRD Data float after PRD PROG high between two consecutive PROG low pulses PRD high between two consecutive PRD low pulses XTAL clock period Symbol Limit Values min. max. - - - - - - - - - - 75 20 - 20 - - 10 ns ns ns ns ns ns ns ns 35 10 10 10 100 0 10 10 100 100 - - 0 - 1 100 2 Unit
tPAW tPMS tPAS tPAH tPCS tPCH tPMS tPMH tPWW tPRW tPAD tPRD tPDH tPDF tPWH1 tPWH2 tCLKP
s
ns ns ns ns ns
s
ns MHz
Data Sheet
83
2003-02
C515C
t PAW PALE t PMS PMSEL1,0 t PAS Port 2 A8-15 t PAH A0-7 H, H
Port 0
D0-7
PROG t PCS Notes: PRD must be high during a programming write cycle. t PWW
t PWH t PCH
MCT03690
Figure 35
Programming Code Byte - Write Cycle Timing
Data Sheet
84
2003-02
C515C
t PAW PALE t PMS PMSEL1,0 t PAS Port 2 A8-15 t PAD Port 0 t PRD PRD t PCS Notes: PROG must be high during a programming read cycle. t PRW t PCH
MCT03689
H, H t PAH A0-7 t PDH D0-7 t PDF t PWH
Figure 36
Verify Code Byte - Read Cycle Timing
Data Sheet
85
2003-02
C515C
PMSEL1,0
H, L
H, L
Port 0
D0, D1 t PCS t PMS t PCH t PMH
D0, D1
PROG t PWW t PMS t PRD t PRW PRD Note: PALE should be low during a lock bit read / write cycle.
t PDH t PDF t PMH
MCT03393
Figure 37
Lock Bit Access Timing
Data Sheet
86
2003-02
C515C
PMSEL1,0
L, H
Port 2
e. g. FD H t PCH
Port 0 t PCS t PRD t PMS PRD
D0-7 t PDH t PDF t PMH
t PRW
Note: PROG must be high during a programming read cycle.
MCT03394
Figure 38
Version Byte - Read Timing
Data Sheet
87
2003-02
C515C
ROM/OTP Verification Characteristics for C515C-8R / C515C-8E ROM Verification Mode 1 (C515C-8R) Parameter Address to valid data Symbol Limit Values min. max. 5 CLP ns - Unit
tAVQV
P1.0 - P1.7 P2.0 - P2.7
Address t AVQV
New Address
Port 0
Data Out
New Data Out Inputs: PSEN = VSS ALE, EA = VIH RESET = VIL2
MCT02764
Data: P0.0 - P0.7 = D0 - D7 Addresses: P1.0 - P1.7 = A0 - A7 P2.0 - P2.7 = A8 - A15
Figure 39
ROM Verification Mode 1
Data Sheet
88
2003-02
C515C
ROM/OTP Verification Mode 2 Parameter ALE pulse width ALE period Data valid after ALE Data stable after ALE P3.5 setup to ALE low Oscillator frequency Symbol min. Limit Values typ. CLP 6 CLP - - max. - - 2 CLP - - 6 ns ns ns ns ns MHz - - - 4 CLP - 4 Unit
tAWD tACY tDVA tDSA tAS
1 / CLP
tCL
-
t ACY t AWD ALE t DSA t DVA Port 0 t AS P3.5
MCT02613
Data Valid
Figure 40
ROM/OTP Verification Mode 2
Data Sheet
89
2003-02
C515C
VDD - 0.5 V
0.2 VDD + 0.9 Test Points 0.2 VDD - 0.1
MCT00039
0.45 V
AC Inputs during testing are driven at VDD - 0.5 V for a logic `1' and 0.45 V for a logic `0'. Timing measurements are made at VIHmin for a logic `1' and VILmax for a logic `0'.
Figure 41
AC Testing: Input, Output Waveforms
VLoad +0.1 V VLoad VLoad -0.1 V Timing Reference Points
VOH -0.1 V
VOL +0.1 V
MCT00038
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs. IOL/IOH 20 mA
Figure 42
AC Testing: Float Waveforms
Crystal/Resonator Oscillator Mode C XTAL1
Driving from External Source
N.C.
XTAL1
2 - 10 MHz C XTAL2 External Oscillator Signal
XTAL2
Crystal Mode : C = 20 pF 10 pF (incl. stray capacitance) Resonator Mode : C = depends on selected ceramic resonator
MCT02765
Figure 43
Data Sheet
Recommended Oscillator Circuits for Crystal Oscillator
90 2003-02
C515C
Package Outlines P-MQFP-80-1 (Plastic Metric Quad Flat Package)
0.25 min 2 +0.1 -0.05 2.45 max
0.65 0.3 0.08 12.35 17.2 14
1)
0.88
C 0.12
0.1
M
A-B D C 80x
0.2 A-B D 80x 0.2 A-B D H 4x D
A
B
14 1) 17.2
80 1 Index Marking
0.6x45
1) Does not include plastic or metal protrusions of 0.25 max per side
7max
H
0.15 +0.08 -0.02
GPM05249
You can find all of our packages, sorts of packing and others in our Infineon Internet Page "Products": http://www.infineon.com/products. SMD = Surface Mounted Device Data Sheet 91 Dimensions in mm 2003-02
www.infineon.com
Published by Infineon Technologies AG

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